Slide #1.

CPE 528: Session #8 Department of Electrical and Computer Engineering University of Alabama in Huntsville
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Slide #2.

Outline  Files  Notes 24/03/19 on VHDL Synthesis UAH-CPE528 2
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Slide #3.

Files  File input/output in VHDL  Used in test benches  Source of test data  Storage for test results  VHDL provides a standard TEXTIO package  read/write 24/03/19 lines of text UAH-CPE528 3
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Slide #4.

Files (cont’d)  VHDL defines a file object, associated types, and certain limited file operations TYPE TYPE file_type file_type IS IS FILE FILE OF OF type_mark; type_mark; PROCEDURE PROCEDURE READ(FILE READ(FILE identifier identifier :: file_type; file_type; value value :: OUT OUT type_mark); type_mark); PROCEDURE PROCEDURE WRITE(FILE WRITE(FILE identifier identifier :: file_type; file_type; value value :: IN IN type_mark); type_mark); FUNCTION FUNCTION ENDFILE(FILE ENDFILE(FILE identifier identifier :: file_type) file_type) RETURN RETURN BOOLEAN; BOOLEAN;  File declarations  VHDL87 FILE FILE identifier identifier :: file_type file_type IS IS [mode] [mode] “file_name”; “file_name”;  VHDL93 FILE FILE identifier identifier :: file_type file_type [[OPEN [[OPEN mode] mode] IS IS “file_name”]; “file_name”]; 24/03/19 UAH-CPE528 4
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Slide #5.

Files (Cont’d) VHDL 87 - files are opened and closed when the associated file object comes into and goes out of scope --- opens opens aa file file for for reading reading FILE FILE in_file:bit_file in_file:bit_file IS IS “my_file.dat” “my_file.dat” --- opens opens aa file file for for writing writing FILE FILE out_file:bit_file out_file:bit_file IS IS OUT OUT “my_other_file.dat”; “my_other_file.dat”; VHDL 93 --- opens opens aa file file for for reading reading FILE FILE in_file:bit_file in_file:bit_file OPEN OPEN READ_MODE READ_MODE IS IS “my_file.dat”; “my_file.dat”; --- Or Or simply simply declared declared (and (and named named and and opened opened later): later): FILE FILE out_file:bit_file; out_file:bit_file; 24/03/19 UAH-CPE528 5
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Slide #6.

File Opening and Closing  In VHDL93, files can be opened in the declaration or predefined procedures can be used: PROCEDURE PROCEDURE FILE_OPEN(FILE FILE_OPEN(FILE identifier:file_type; identifier:file_type; file_name: IN STRING; file_name: IN STRING; open_kind: open_kind: FILE_OPEN_KIND FILE_OPEN_KIND := := READ_MODE); READ_MODE); PROCEDURE PROCEDURE FILE_OPEN(status: FILE_OPEN(status: OUT OUT FILE_OPEN_STATUS; FILE_OPEN_STATUS; FILE identifier: file_type; FILE identifier: file_type; file_name: file_name: IN IN STRING; STRING; open_kind: FILE_OPEN_KIND open_kind: FILE_OPEN_KIND := := READ_MODE); READ_MODE); PROCEDURE PROCEDURE FILE_CLOSE(FILE FILE_CLOSE(FILE identifier: identifier: file_type); file_type);   The values for FILE_OPEN_KIND are: READ_MODE, WRITE_MODE, and APPEND_MODE The values for FILE_OPEN_STATUS are: OPEN_OK, STATUS_ERROR, NAME_ERROR, and MODE_ERROR 24/03/19 UAH-CPE528 6
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Slide #7.

Text Input and Output Basic file operations in VHDL are limited to unformatted input/output  VHDL includes the TEXTIO package for input and output of ASCII text   TEXTIO is located in the STD library USE USE STD.TEXTIO.ALL; STD.TEXTIO.ALL;  The following data types are supported by the TEXTIO routines:      Bit, Bit_vector Boolean Character, String Integer, Real Time 24/03/19 UAH-CPE528 7
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Slide #8.

TEXTIO Procedures  TEXTIO defines a LINE data type    All read and write operations use the LINE type TEXTIO also defines a FILE type of TEXT for use with ASCII text Procedures defined by TEXTIO are:  READLINE(f,k)   READ(k,v,...)   writes value v to LINE k WRITELINE(f,k)   reads a value of v of its type from k WRITE(k,v,...)   reads a line of file f and places it in buffer k writes k to file f ENDFILE(f) returns TRUE at the end of FILE 24/03/19 UAH-CPE528 8
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Slide #9.

Using TEXTIO  Reading from a file  READLINE reads a line from the file into a LINE buffer  READ gets data from the buffer  Writing to a file  WRITE puts data into a LINE buffer  WRITELINE writes the data in the LINE buffer to file  READ and WRITE have several formatting parameters  Right or left justification  Field width  Unit displayed (for time) 24/03/19 UAH-CPE528 9
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Slide #10.

TEXTIO: Example 1  This procedure displays the current state of a FSM USE USE STD.TEXTIO.ALL; STD.TEXTIO.ALL; --TEXTIO --TEXTIO package package is is available available TYPE TYPE state state IS IS (reset, (reset, good); good); -- new new type type state state is is declared declared PROCEDURE PROCEDURE display_state display_state (current_state (current_state :: IN IN state) state) IS IS VARIABLE k : LINE; -buffer k of type LINE VARIABLE k : LINE; -- buffer k of type LINE --- file file flush flush is is of of type type TEXT TEXT and and will will output output to to console console FILE FILE flush flush :: TEXT TEXT IS IS OUT OUT "/dev/tty"; "/dev/tty"; VARIABLE VARIABLE state_string state_string :: STRING(1 STRING(1 to to 7); 7); --- text text value value BEGIN BEGIN CASE CASE current_state current_state IS IS WHEN WHEN reset reset => => state_string state_string := := "reset "reset "; "; WHEN WHEN good good => => state_string state_string := := "good "good "; "; END END CASE; CASE; WRITE WRITE (k, (k, state_string, state_string, LEFT, LEFT, 7); 7); --left --left justified, justified, 7s 7s WRITELINE (flush, k); -send buffer to file flush WRITELINE (flush, k); -- send buffer to file flush END END display_state; display_state; If we call this procedure again ... 24/03/19 UAH-CPE528 10
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Slide #11.

TextIO: Read_v1d procedure read_v1d (variable f :in text ; v : out std_logic_vector ) is variable buf : line; variable c : character ; begin -- do not forget appropriate library declarations readline (f , buf ); --read a line from the file. for i in v ’range loop read( buf , c ) ; --read a character from the line. case c is when ‘ X ’ => v (i) := ‘ X ’ ; when ‘ U ’ => v (i) := ‘ U ’ ; when ‘ Z ’ => v (i) := ‘ Z ’ ; when ‘ 0 ’ => v (i) := ‘ 0 ’ ; when ‘ 1 ’ => v (i) := ‘ 1 ’ ; when ‘ -’ => v (i):= ‘ -’ ; when ‘ W ’ => v (i) := ‘ W ’ ; when ‘ L ’ => v (i) := ‘ L ’ ; when ‘ H ’ => v (i) := ‘ H ’ ; when others => v (i) := ‘ 0 ’; end case; end loop; end; 24/03/19 UAH-CPE528 11
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Slide #12.

Longer TextIO example LIBRARY IEEE; USE STD.TEXTIO.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE IEEE.STD_LOGIC_1164.ALL; ENTITY square IS PORT( go : IN std_logic); END square; -- square the value int_val := int_val **2; ARCHITECTURE simple OF square IS BEGIN PROCESS(go) FILE infile : TEXT IS IN "/pp/test/example1"; FILE outfile : TEXT IS OUT "/pp/test/outfile1"; VARIABLE out_line, my_line : LINE; VARIABLE int_val : INTEGER; BEGIN WHILE NOT( ENDFILE(infile)) LOOP -- read a line from the input file READLINE( infile, my_line); -- write the squared value to the line WRITE( out_line, int_val); -- write the line to the output file WRITELINE( outfile, out_line); END LOOP; END PROCESS; END simple; -- read a value from the line READ( my_line, int_val); 24/03/19 UAH-CPE528 12
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Slide #13.

An Example  Procedure to read data from a file and store the data in a memory array  Format of the data in the file  address N comments byte1 byte2 ... byteN comments address – 4 hex digits  N – indicates the number of bytes of code  bytei - 2 hex digits  each byte is separated by one space  the last byte must be followed by a space  anything following the last state will not be read and will be treated as a comment  24/03/19 UAH-CPE528 13
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Slide #14.

An Example (cont’d)  Code sequence: an example   TEXTIO does not include read procedure for hex numbers   12AC 7 (7 hex bytes follow) AE 03 B6 91 C7 00 0C (LDX imm, LDA dir, STA ext) 005B 2 (2 bytes follow) 01 FC_ we will read each hex value as a string of characters and then convert the string to an integer How to implement conversion?    24/03/19 table lookup – constant named lookup is an array of integers indexed by characters in the range ‘0’ to ‘F’ this range includes the 23 ASCII characters: ‘0’, ‘1’, ... ‘9’, ‘:’, ‘;’, ‘<‘, ‘=‘, ‘>’, ‘?’, ‘@’, ‘A’, ... ‘F’ corresponding values: 0, 1, ... 9, -1, -1, -1, -1, -1, -1, -1, 10, 11, 12, 13, 14, 15 UAH-CPE528 14
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Slide #15.

VHDL Code to Fill Memory Array 24/03/19 UAH-CPE528 15
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Slide #16.

VHDL Code to Fill Memory Array (cont’d) 24/03/19 UAH-CPE528 16
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Slide #17.

Notes on VHDL Synthesis Department of Electrical and Computer Engineering University of Alabama in Huntsville
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Slide #18.

Outline  VHDL Packages for Synthesis  VHDL for Combinational Logic Synthesis  VHDL for Sequential Logic Synthesis  VHDL for RTL Level Synthesis  Structural VHDL  Implementation Technology Considerations  Summary 24/03/19 UAH-CPE528
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Slide #19.

VHDL Packages for Synthesis Base Types  Standard bit types may be used  Typically IEEE 1164 Std. types are used  std_ulogic type  USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL; Values ‘U’, ‘X’, ‘W’, and ‘-’ are called metalogical values for synthesis TYPE TYPE std_ulogic std_ulogic IS IS (( 'U', 'U', 'X', 'X', '0', '0', '1', '1', 'Z', 'Z', 'W', 'W', 'L', 'L', 'H', 'H', '-' '-' ); );  std_logic 24/03/19 --- Uninitialized Uninitialized -Forcing -- Forcing Unknown Unknown -Forcing 0 -- Forcing 0 --- Forcing Forcing 11 --- High High Impedance Impedance -Unknown -- Weak Weak Unknown -Weak 0 -- Weak 0 -Weak 1 -- Weak 1 -Don't care -- Don't care type - resolved std_ulogic type UAH-CPE528
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Slide #20.

VHDL Packages for Synthesis Base Types (cont.)  The std_logic_1164 package also contains: Vectors of std_ulogic and std_logic  Subtypes of std_logic - X01, X01Z, UX01, UX10Z  Logic functions with various arguments - std_ulogic, std_logic, std_logic_vector  FUNCTION FUNCTION “and” “and” (l,r (l,r :: std_ulogic;) std_ulogic;) RETURN RETURN UX01; UX01; FUNCTION FUNCTION “nand” “nand” (l,r (l,r :: std_ulogic;) std_ulogic;) RETURN RETURN UX01; UX01; FUNCTION “or” (l,r : std_ulogic;) RETURN UX01; FUNCTION “or” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nor” (l,r FUNCTION “nor” (l,r :: std_ulogic;) std_ulogic;) RETURN RETURN UX01; UX01; FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01; FUNCTION FUNCTION “xnor” “xnor” (l,r (l,r :: std_ulogic;) std_ulogic;) return return ux01; ux01; FUNCTION FUNCTION "not" "not" (l,r (l,r :: std_ulogic) std_ulogic) RETURN RETURN UX01; UX01;  Conversion functions FUNCTION FUNCTION To_bit(s:std_ulogic) To_bit(s:std_ulogic) RETURN RETURN bit; bit; FUNCTION To_bitvector(s:std_ulogic_vector) FUNCTION To_bitvector(s:std_ulogic_vector) RETURN RETURN bit_vector; bit_vector; FUNCTION To_StdULogic(b:bit) RETURN std_ulogic; FUNCTION To_StdULogic(b:bit) RETURN std_ulogic; 24/03/19 UAH-CPE528
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Slide #21.

VHDL Packages for Synthesis Base Types (cont.)  Clock edge functions FUNCTION FUNCTION rising_edge rising_edge (SIGNAL (SIGNAL s:std_ulogic) s:std_ulogic) RETURN RETURN boolean; boolean; FUNCTION FUNCTION falling_edge falling_edge (SIGNAL (SIGNAL s:std_ulogic) s:std_ulogic) RETURN RETURN boolean; boolean; Unknown functions FUNCTION FUNCTION Is_X Is_X (s:std_ulogic_vector) (s:std_ulogic_vector) RETURN RETURN boolean; boolean; FUNCTION Is_X (s:std_logic_vector) RETURN boolean; FUNCTION Is_X (s:std_logic_vector) RETURN boolean; FUNCTION FUNCTION Is_X Is_X (s:std_ulogic) (s:std_ulogic) RETURN RETURN boolean; boolean; 24/03/19 UAH-CPE528
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Slide #22.

VHDL Packages for Synthesis Arithmetic Packages   All synthesis tools support some type of arithmetic packages Synopsis developed packages based on std_logic_1164 package - supported by many other synthesis tools     Actel synthesis tools support their own package   std_logic_arith std_logic_signed std_logic_unsigned asyl.arith IEEE has developed standard packages for synthesis IEEE Std. 1076.3   Numeric_Bit Numeric_Std 24/03/19 UAH-CPE528 22
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Slide #23.

IEEE Std 1076.3 Packages Numeric_Bit  Type declarations for signed and unsigned numbers USE USE IEEE.numeric_bit.ALL; IEEE.numeric_bit.ALL; TYPE TYPE unsigned unsigned IS IS ARRAY ARRAY (natural (natural RANGE RANGE <> <> )) OF OF bit; bit; TYPE signed IS ARRAY (natural RANGE <> ) OF bit; TYPE signed IS ARRAY (natural RANGE <> ) OF bit;  Arithmetic operators - various combinations of signed and unsigned arguments FUNCTION FUNCTION “abs” “abs” (arg:unsigned) (arg:unsigned) RETURN RETURN unsigned; unsigned; FUNCTION “-” (arg:unsigned) RETURN unsigned; FUNCTION “-” (arg:unsigned) RETURN unsigned; FUNCTION FUNCTION “+” “+” (l,r:unsigned) (l,r:unsigned) RETURN RETURN unsigned; unsigned; FUNCTION “-” (l,r:unsigned) RETURN unsigned; FUNCTION “-” (l,r:unsigned) RETURN unsigned; FUNCTION FUNCTION “*” “*” (l,r:unsigned) (l,r:unsigned) RETURN RETURN unsigned; unsigned; FUNCTION “/” (l,r:unsigned) RETURN unsigned; FUNCTION “/” (l,r:unsigned) RETURN unsigned; FUNCTION FUNCTION “rem” “rem” (l,r:unsigned) (l,r:unsigned) RETURN RETURN unsigned; unsigned; FUNCTION “mod” (l,r:unsigned) RETURN unsigned; FUNCTION “mod” (l,r:unsigned) RETURN unsigned; 24/03/19 UAH-CPE528 23
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Slide #24.

IEEE Std 1076.3 Packages Numeric_Bit  Comparison operators - various combinations of signed and unsigned arguments FUNCTION FUNCTION “>” “>” (l,r:unsigned) (l,r:unsigned) RETURN RETURN boolean; boolean; FUNCTION “<” (l,r:unsigned) RETURN boolean; FUNCTION “<” (l,r:unsigned) RETURN boolean; FUNCTION FUNCTION “<=” “<=” (l,r:unsigned) (l,r:unsigned) RETURN RETURN boolean; boolean; FUNCTION “>=” (l,r:unsigned) RETURN boolean; FUNCTION “>=” (l,r:unsigned) RETURN boolean; FUNCTION FUNCTION “=” “=” (l,r:unsigned) (l,r:unsigned) RETURN RETURN boolean; boolean; FUNCTION FUNCTION “/=” “/=” (l,r:unsigned) (l,r:unsigned) RETURN RETURN boolean; boolean;  Shift and rotate functions FUNCTION FUNCTION shift_left shift_left (arg:unsigned; (arg:unsigned; count:natural) count:natural) RETURN RETURN unsigned; unsigned; FUNCTION shift_right (arg:unsigned; count:natural) RETURN FUNCTION shift_right (arg:unsigned; count:natural) RETURN unsigned; unsigned; FUNCTION rotate_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION FUNCTION rotate_right rotate_right (arg:unsigned; (arg:unsigned; count:natural) count:natural) RETURN RETURN unsigned; unsigned; FUNCTION FUNCTION sll sll (arg:unsigned; (arg:unsigned; count:natural) count:natural) RETURN RETURN unsigned; unsigned; FUNCTION slr (arg:unsigned; count:natural) RETURN unsigned; FUNCTION slr (arg:unsigned; count:natural) RETURN unsigned; FUNCTION FUNCTION rol rol (arg:unsigned; (arg:unsigned; count:natural) count:natural) RETURN RETURN unsigned; unsigned; FUNCTION ror (arg:unsigned; count:natural) RETURN unsigned; FUNCTION ror (arg:unsigned; count:natural) RETURN unsigned; 24/03/19 UAH-CPE528 24
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Slide #25.

IEEE Std 1076.3 Packages Numeric_Bit  Resize functions FUNCTION FUNCTION resize resize (arg:unsigned;new_size:natural) (arg:unsigned;new_size:natural) RETURN RETURN unsigned; unsigned; FUNCTION resize (arg:signed;new_size:natural) RETURN signed; FUNCTION resize (arg:signed;new_size:natural) RETURN signed;  Conversion functions FUNCTION FUNCTION to_integer to_integer (arg:unsigned) (arg:unsigned) RETURN RETURN natural; natural; FUNCTION to_unsigned (arg,size:natural) RETURN FUNCTION to_unsigned (arg,size:natural) RETURN unsigned; unsigned;  Logical operators FUNCTION FUNCTION “not” “not” (l:unsigned) (l:unsigned) RETURN RETURN unsigned; unsigned; FUNCTION “and” (l,r:unsigned) RETURN FUNCTION “and” (l,r:unsigned) RETURN unsigned; unsigned; FUNCTION FUNCTION “or” “or” (l,r:unsigned) (l,r:unsigned) RETURN RETURN unsigned; unsigned; FUNCTION “nand” (l,r:unsigned) RETURN FUNCTION “nand” (l,r:unsigned) RETURN unsigned; unsigned; FUNCTION “nor” (l,r:unsigned) RETURN unsigned; FUNCTION “nor” (l,r:unsigned) RETURN unsigned; FUNCTION FUNCTION “xnor” “xnor” (l,r:unsigned) (l,r:unsigned) RETURN RETURN unsigned; unsigned;  Edge detection functions FUNCTION FUNCTION rising_edge(SIGNAL rising_edge(SIGNAL s:bit) s:bit) RETURN RETURN boolean; boolean; FUNCTION falling_edge(SIGNAL s:bit) RETURN FUNCTION falling_edge(SIGNAL s:bit) RETURN boolean; boolean; 24/03/19 UAH-CPE528 25
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Slide #26.

IEEE Std 1076.3 Packages Numeric_Std USE USE IEEE.numeric_std.ALL; IEEE.numeric_std.ALL;  Similar to Numeric_Bit package using std_logic_1164 types         Signed and unsigned type declarations Aritmetic operators Comparison operators Shift and rotate functions Resize functions Conversion functions Logical operators Match functions FUNCTION FUNCTION std_match std_match (l,r:std_ulogic) (l,r:std_ulogic) RETURN RETURN boolean; boolean; FUNCTION std_match (l,r:unsigned) RETURN boolean; FUNCTION std_match (l,r:unsigned) RETURN boolean;  Translation functions FUNCTION FUNCTION to_01 to_01 (s:unsigned; (s:unsigned; xmap:std_logic xmap:std_logic := := ‘0’) ‘0’) RETURN RETURN unsigned; unsigned; 24/03/19 UAH-CPE528 26
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Slide #27.

Outline  VHDL Packages for Synthesis  VHDL for Combinational Logic Synthesis                 Types Attributes Concurrent signal assignment statements Operators Processes If statements Case statements Loops Procedures and functions Tri state logic Use of don’t cares After clauses Inferring latches Problems to avoid VHDL for Sequential Logic Synthesis VHDL for RTL Level Synthesis 24/03/19 UAH-CPE528
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Slide #28.

Types  Scalar types  Enumeration types are supported      Integer type, Natural, and Positive are supported    Bit, Boolean, and Std_Ulogic map to single bits Mapping of other types will be made by the tool unless the ENUM_ENCODING attribute is used Character type is suppored Severity_level type is ignored A subtype with a descrete range should be used or the default 32 bit length will be synthesized Physical types (e.g., time) are ignored Floating point type is ignored - references to floating point objects can occur only within ignored constructs, e.g., After clauses, etc. 24/03/19 UAH-CPE528 28
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Slide #29.

Types (cont.)  Array types are supported   Bounds must be specified directly or indirectly as static values of an integer type Element subtype must denote a scalar type or a one dimensional vector of an enumerated type that denotes single bits TYPE TYPE integer_array integer_array IS IS ARRAY(natural ARRAY(natural RANGE RANGE 77 DOWNTO DOWNTO 0) 0) OF OF integer; integer; TYPE TYPE boolean_array boolean_array IS IS ARRAY(integer ARRAY(integer RANGE RANGE <>) <>) OF OF boolean; boolean; ... ... SIGNAL SIGNAL bool_sig bool_sig :: boolean_array(-1 boolean_array(-1 to to 1); 1);    Record types are supported Access types are ignored File types are ignored  File objects and file operations are not supported 24/03/19 UAH-CPE528 29
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Slide #30.

Attributes  The following predefined attributes for types are supported:       The following predefined attributes for array objects are supported:         a’LEFT a’RIGHT a’HIGH a’LOW a’RANGE a’REVERSE_RANGE a’LENGTH The following predefined attributes for signals are supported    t’BASE t’LEFT t’RIGHT t’HIGH t’LOW s’STABLE s’EVENT User defined attributes other than ENUM_ENCODING are NOT supported 24/03/19 UAH-CPE528 30
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Slide #31.

Concurrent Signal Assignment Statements  Simple concurrent signal assignment statements are supported library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY csa csa is is PORT(a : IN PORT(a : IN std_logic; std_logic; bb :: IN std_logic; IN std_logic; yy :: OUT OUT std_logic); std_logic); END csa; END csa; ARCHITECTURE ARCHITECTURE behavior behavior OF OF csa csa IS IS BEGIN BEGIN yy <= <= aa NOR NOR b; b; END behavior; END behavior; 24/03/19 library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY aoi_csa aoi_csa is is PORT(a : IN std_logic; PORT(a : IN std_logic; bb :: IN IN std_logic; std_logic; cc :: IN std_logic; IN std_logic; yy :: OUT OUT std_logic); std_logic); END aoi_csa; END aoi_csa; ARCHITECTURE ARCHITECTURE behavior behavior OF OF aoi_csa aoi_csa IS IS SIGNAL sig1,sig2 : std_logic; SIGNAL sig1,sig2 : std_logic; BEGIN BEGIN sig1 sig1 <= <= aa AND AND b; b; sig2 <= c OR sig1; sig2 <= c OR sig1; yy <= <= NOT NOT sig2; sig2; END behavior; END behavior; UAH-CPE528 31
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Slide #32.

Conditional Signal Assignment Statements  Concurrent conditional signal assignment statements are supported - must end in else clause library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY mux2 mux2 is is PORT(a : PORT(a : IN IN std_logic; std_logic; bb :: IN std_logic; IN std_logic; sel : IN sel : IN std_logic; std_logic; yy :: OUT OUT std_logic); std_logic); END mux2; END mux2; ARCHITECTURE ARCHITECTURE behavior behavior OF OF mux2 mux2 IS IS BEGIN BEGIN yy <= <= aa WHEN WHEN (sel (sel == '0') '0') ELSE ELSE bb WHEN (sel = '1') ELSE WHEN (sel = '1') ELSE 'X'; 'X'; END behavior; END behavior; 24/03/19 UAH-CPE528 32
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Slide #33.

Selected Signal Assignment Statements  Concurrent selected signal assignment statements are supported library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY mux4 mux4 is is PORT(a : PORT(a : IN IN std_logic; std_logic; bb :: IN std_logic; IN std_logic; cc :: IN IN std_logic; std_logic; dd :: IN std_logic; IN std_logic; sel : IN sel : IN std_logic_vector(1 std_logic_vector(1 DOWNTO DOWNTO 0); 0); yy :: OUT std_logic); OUT std_logic); END mux4; END mux4; ARCHITECTURE ARCHITECTURE behavior behavior OF OF mux4 mux4 IS IS BEGIN BEGIN WITH WITH sel sel SELECT SELECT yy <= a WHEN <= a WHEN "00", "00", bb WHEN "01", WHEN "01", cc WHEN WHEN "10", "10", dd WHEN "11", WHEN "11", 'X' WHEN 'X' WHEN OTHERS; OTHERS; END behavior; END behavior; 24/03/19 UAH-CPE528 33
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Slide #34.

Operators  Generally, if the numeric_bit and numeric_std packages are supported, the operators within them are supported  Arithmetic operators - “abs”, “+”, “-”, “*”, “/”, “rem”, “mod” library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; use use IEEE.numeric_std.all; IEEE.numeric_std.all; ENTITY ENTITY divider divider is is PORT(divisor PORT(divisor :: IN IN unsigned(1 unsigned(1 DOWNTO DOWNTO 0); 0); dividend : IN unsigned(1 DOWNTO 0); dividend : IN unsigned(1 DOWNTO 0); quotient quotient :: OUT OUT unsigned(1 unsigned(1 DOWNTO DOWNTO 0)); 0)); END divider; END divider; ARCHITECTURE ARCHITECTURE behavior behavior OF OF divider divider IS IS BEGIN BEGIN quotient quotient <= <= dividend dividend // divisor; divisor; END behavior; END behavior; 24/03/19 UAH-CPE528 34
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Slide #35.

Operators (cont.)  Comparison operators - “>”, “<“, “<=“, “>=“, “=“, “/=“ library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; use use IEEE.numeric_std.all; IEEE.numeric_std.all; ENTITY ENTITY compare compare is is PORT(a : IN PORT(a : IN unsigned(3 unsigned(3 DOWNTO DOWNTO 0); 0); bb :: IN unsigned(3 DOWNTO 0); IN unsigned(3 DOWNTO 0); aleb : OUT aleb : OUT boolean); boolean); END compare; END compare; ARCHITECTURE ARCHITECTURE behavior behavior OF OF compare compare IS IS BEGIN BEGIN aleb aleb <= <= (a (a <= <= b); b); END behavior; END behavior; 24/03/19 UAH-CPE528 35
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Slide #36.

Operators (cont.)  Shift and conversion operators - “shift_left”, “shift_right”, “rotate_left”, “rotate_right”, “resize”, “to_integer”, “to_unsigned” library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; use use IEEE.numeric_std.all; IEEE.numeric_std.all; ENTITY ENTITY shift_4 shift_4 is is PORT(a : IN PORT(a : IN unsigned(3 unsigned(3 DOWNTO DOWNTO 0); 0); bb :: IN unsigned(1 DOWNTO 0); IN unsigned(1 DOWNTO 0); yy :: OUT OUT unsigned(3 unsigned(3 DOWNTO DOWNTO 0)); 0)); END shift_4; END shift_4; ARCHITECTURE ARCHITECTURE behavior behavior OF OF shift_4 shift_4 IS IS BEGIN BEGIN yy <= <= shift_left(a,to_integer(b)); shift_left(a,to_integer(b)); END behavior; END behavior; 24/03/19 UAH-CPE528 36
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Slide #37.

Process Statements    Process statements are supported Postponed processes (or postponed concurrent signal assignment statements) are NOT supported Process statement can have either a sensitivity list or a WAIT statement    Sensitivity list is ignored for synthesis (by most tools) thus, to avoid simulation mismatches, all signals which appear on the RHS should be in the sensitivity list Only one WAIT statement per process is allowed and it must be the first statement in the process after BEGIN Only the WAIT UNTIL syntax of the WAIT statement is supported WAIT WAIT UNTIL UNTIL input1 input1 == ‘1’; ‘1’; WAIT UNTIL clock’EVENT WAIT UNTIL clock’EVENT and and clock clock == ‘1’; ‘1’; 24/03/19 UAH-CPE528 37
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Slide #38.

Process Statements Example library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY aoi_process aoi_process is is PORT(a : IN std_logic; PORT(a : IN std_logic; bb :: IN IN std_logic; std_logic; cc :: IN std_logic; IN std_logic; yy :: OUT OUT std_logic); std_logic); END aoi_process; END aoi_process; ARCHITECTURE ARCHITECTURE behavior behavior OF OF aoi_process aoi_process IS IS SIGNAL sig1 : std_logic; SIGNAL sig1 : std_logic; BEGIN BEGIN comb comb :: PROCESS(a,b,c,sig1) PROCESS(a,b,c,sig1) BEGIN BEGIN sig1 sig1 <= <= aa AND AND b; b; yy <= not(sig1 or <= not(sig1 or c); c); END PROCESS comb; END PROCESS comb; END behavior; END behavior; 24/03/19 UAH-CPE528 38
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Slide #39.

Process Statements Incomplete Sensitivity List library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY aoi_process aoi_process is is PORT(a : IN std_logic; PORT(a : IN std_logic; bb :: IN IN std_logic; std_logic; cc :: IN std_logic; IN std_logic; yy :: OUT OUT std_logic); std_logic); END aoi_process; END aoi_process; a b ARCHITECTURE ARCHITECTURE behavior behavior OF OF aoi_process aoi_process IS IS SIGNAL sig1 : std_logic; SIGNAL sig1 : std_logic; BEGIN BEGIN comb comb :: PROCESS(a,b,c) PROCESS(a,b,c) BEGIN BEGIN sig1 sig1 <= <= aa AND AND b; b; yy <= not(sig1 or <= not(sig1 or c); c); END PROCESS comb; END PROCESS comb; END behavior; END behavior; 24/03/19 0 c sig1 U y UAH-CPE528 0 5 10 15 20 39
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Slide #40.

Sequential Signal Assignment Statements  Various types of signal assignment statements inside a process statement (sequential signal assignment statements) are supported statements  Case statements  Loop statement  IF Only For loops supported  Bounds must be specified as static values of an integer type  Exit and Next statements supported (without lables)  24/03/19 UAH-CPE528 40
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Slide #41.

Sequential IF Statements  IF statements are supported library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY xor_process xor_process is is PORT(a : IN std_logic; PORT(a : IN std_logic; bb :: IN IN std_logic; std_logic; yy :: OUT std_logic); OUT std_logic); END xor_process; END xor_process; ARCHITECTURE ARCHITECTURE behavior behavior OF OF xor_process xor_process IS IS BEGIN BEGIN comb comb :: PROCESS(a,b) PROCESS(a,b) BEGIN BEGIN IF((a IF((a == '1' '1' and and bb == '0') '0') OR OR (a = '0' and b = '1')) (a = '0' and b = '1')) THEN THEN yy <= '1'; <= '1'; ELSE ELSE yy <= <= '0'; '0'; END IF; END IF; END PROCESS END PROCESS comb; comb; END behavior; END behavior; 24/03/19 UAH-CPE528 41
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Slide #42.

Sequential Case Statements library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;  Case statements are supported  ENTITY ENTITY mux4_process mux4_process is is PORT(a PORT(a :: IN IN std_logic; std_logic; bb :: IN std_logic; IN std_logic; cc :: IN IN std_logic; std_logic; dd :: IN std_logic; IN std_logic; sel : IN sel : IN std_logic_vector(1 std_logic_vector(1 DOWNTO DOWNTO 0); 0); yy :: OUT std_logic); OUT std_logic); END mux4_process; END mux4_process; Choices which include metalogical values are never taken ARCHITECTURE ARCHITECTURE behavior behavior OF OF mux4_process mux4_process IS IS BEGIN BEGIN comb comb :: PROCESS(a,b,c,d,sel) PROCESS(a,b,c,d,sel) BEGIN BEGIN CASE CASE sel sel IS IS WHEN "00" WHEN "00" => => yy <= <= a; a; WHEN "01" => y <= b; WHEN "01" => y <= b; WHEN WHEN "10" "10" => => yy <= <= c; c; WHEN "11" => y <= d; WHEN "11" => y <= d; WHEN WHEN OTHERS OTHERS => => yy <= <= 'X'; 'X'; END CASE; END CASE; END PROCESS END PROCESS comb; comb; END behavior; END behavior; 24/03/19 UAH-CPE528 42
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Slide #43.

Sequential Loop Statements  Only For loops with integer range are supported library library IEEE; IEEE; use use IEEE.std_logic_1164.all; IEEE.std_logic_1164.all; ENTITY ENTITY shift4 shift4 is is PORT(mode :: IN PORT(mode IN std_logic; std_logic; shift_in : IN std_logic; shift_in : IN std_logic; aa :: IN 1); IN std_logic_vector(4 std_logic_vector(4 DOWNTO DOWNTO 1); ARCHITECTURE behavior ARCHITECTURE behavior OF OF shift4 shift4 IS IS yy :: OUT std_logic_vector(4 DOWNTO 1); OUT std_logic_vector(4 DOWNTO 1); in_temp : std_logic_vector(5 DOWNTO 0); SIGNAL SIGNAL in_temp : std_logic_vector(5 DOWNTO 0); shift_out shift_out :: OUT OUT std_logic); std_logic); SIGNAL SIGNAL out_temp out_temp :: std_logic_vector(5 std_logic_vector(5 DOWNTO DOWNTO 1); 1); END END shift4; shift4; BEGIN BEGIN in_temp(0) in_temp(0) <= <= shift_in; shift_in; in_temp(4 in_temp(4 DOWNTO DOWNTO 1) 1) <= <= a; a; in_temp(5) <= '0'; in_temp(5) <= '0'; comb comb :: PROCESS(mode,in_temp,a) PROCESS(mode,in_temp,a) BEGIN BEGIN FOR FOR ii IN IN 11 TO TO 55 LOOP LOOP IF(mode = '0') IF(mode = '0') THEN THEN out_temp(i) <= out_temp(i) <= in_temp(i-1); in_temp(i-1); ELSE ELSE out_temp(i) out_temp(i) <= <= in_temp(i); in_temp(i); END END IF; IF; END LOOP; END LOOP; END PROCESS END PROCESS comb; comb; yy <= <= out_temp(4 out_temp(4 DOWNTO DOWNTO 1); 1); shift_out <= out_temp(5); shift_out <= out_temp(5); END END behavior; behavior; 24/03/19 UAH-CPE528 43
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Slide #44.

Procedures and Functions  Procedures and Functions are supported - with limitations to allowed statement types  Procedures and functions may be in a package or in the declarative part of the architecture LIBRARY LIBRARY ieee; ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all; USE USE ieee.numeric_std.all; ieee.numeric_std.all; PACKAGE PACKAGE logic_package logic_package IS IS FUNCTION FUNCTION majority(in1, majority(in1, in2, in2, in3 in3 :: std_logic) std_logic) RETURN RETURN std_logic; std_logic; PROCEDURE PROCEDURE decode(SIGNAL decode(SIGNAL input input :: IN IN std_logic_vector(1 std_logic_vector(1 DOWNTO DOWNTO 0); 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)); 0)); END END logic_package; logic_package; 24/03/19 UAH-CPE528 44
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Slide #45.

Procedures and Functions (cont.) PACKAGE PACKAGE BODY BODY logic_package logic_package IS IS FUNCTION FUNCTION majority(in1, majority(in1, in2, in2, in3 in3 :: std_logic) std_logic) RETURN RETURN std_logic std_logic IS IS VARIABLE result : std_logic; VARIABLE result : std_logic; BEGIN BEGIN IF((in1 IF((in1 == '1' '1' and and in2 in2 == '1') '1') or or (in2 (in2 == '1' '1' and and in3 in3 == '1') '1') or or (in1 = '1' and in3 = '1')) THEN (in1 = '1' and in3 = '1')) THEN result result := := '1'; '1'; ELSIF((in1 = ELSIF((in1 = '0' '0' and and in2 in2 == '0') '0') or or (in2 (in2 == '0' '0' and and in3 in3 == '0') '0') or or (in1 = '0' and in3 = '0')) THEN (in1 = '0' and in3 = '0')) THEN result result := := '0'; '0'; ELSE ELSE result result := := 'X'; 'X'; END IF; END IF; RETURN RETURN result; result; END majority; END majority; 24/03/19 UAH-CPE528 45
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Slide #46.

Procedures and Functions (cont.) PROCEDURE PROCEDURE decode(SIGNAL decode(SIGNAL input input :: IN IN std_logic_vector(1 std_logic_vector(1 DOWNTO DOWNTO 0); 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)) 0)) IS IS BEGIN BEGIN CASE CASE input input IS IS WHEN "00" WHEN "00" => => output <= output <= "0001"; "0001"; WHEN "01" => WHEN "01" => output output <= <= "0010"; "0010"; WHEN "10" => WHEN "10" => output output <= <= "0100"; "0100"; WHEN "11" => WHEN "11" => output output <= <= "1000"; "1000"; WHEN OTHERS => WHEN OTHERS => output output <= <= "XXXX"; "XXXX"; END CASE; END CASE; END END decode; decode; END END logic_package; logic_package; 24/03/19 UAH-CPE528 46
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Slide #47.

Using Procedures and Functions LIBRARY LIBRARY ieee; ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all; USE USE ieee.numeric_std.all; ieee.numeric_std.all; USE work.logic_package.all; USE work.logic_package.all; ENTITY ENTITY voter voter IS IS PORT(a : IN PORT(a : IN std_logic; std_logic; bb :: IN std_logic; IN std_logic; cc :: IN IN std_logic; std_logic; yy :: OUT std_logic); OUT std_logic); END voter; END voter; ARCHITECTURE ARCHITECTURE maj maj OF OF voter voter IS IS BEGIN BEGIN yy <= <= majority(a,b,c); majority(a,b,c); END maj; END maj; 24/03/19 UAH-CPE528 47
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Slide #48.

Using Procedures and Functions (cont.) LIBRARY LIBRARY ieee; ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all; USE USE ieee.numeric_std.all; ieee.numeric_std.all; USE work.logic_package.all; USE work.logic_package.all; ENTITY ENTITY decoder decoder IS IS PORT(y : IN std_logic_vector(1 PORT(y : IN std_logic_vector(1 DOWNTO DOWNTO 0); 0); gg :: OUT std_logic_vector(3 DOWNTO OUT std_logic_vector(3 DOWNTO 0)); 0)); END decoder; END decoder; ARCHITECTURE ARCHITECTURE dec dec OF OF decoder decoder IS IS BEGIN BEGIN comb comb :: PROCESS(y) PROCESS(y) BEGIN BEGIN decode(y,g); decode(y,g); END PROCESS END PROCESS comb; comb; END dec; END dec; 24/03/19 UAH-CPE528 48
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Slide #49.

Tri-State Logic  Tri-state logic is infered when an object is assigned an IEEE Std. 1164 value ‘Z’ library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY tri_state4 tri_state4 is is PORT(enable : IN PORT(enable : IN std_logic; std_logic; aa :: IN std_logic_vector(3 IN std_logic_vector(3 DOWNTO DOWNTO 0); 0); yy :: OUT std_logic_vector(3 DOWNTO 0)); OUT std_logic_vector(3 DOWNTO 0)); END tri_state4; END tri_state4; ARCHITECTURE ARCHITECTURE behavior behavior OF OF tri_state4 tri_state4 IS IS BEGIN BEGIN yy <= <= aa WHEN WHEN (enable (enable == '1') '1') ELSE ELSE "ZZZZ"; "ZZZZ"; END behavior; END behavior; 24/03/19 UAH-CPE528 49
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Slide #50.

Use of Don’t Cares (‘X’s)  IEEE Std. 1164 values of ‘X’ or ‘-’ can be used to specify “don’t care” conditions library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY not_xor not_xor is is PORT(a : IN std_logic; PORT(a : IN std_logic; bb :: IN IN std_logic; std_logic; yy :: OUT std_logic); OUT std_logic); END not_xor; END not_xor; ARCHITECTURE ARCHITECTURE behavior behavior OF OF not_xor not_xor IS IS BEGIN BEGIN comb comb :: PROCESS(a,b) PROCESS(a,b) BEGIN BEGIN IF((a IF((a == '1' '1' and and bb == '0') '0') OR OR (a = '0' and b = '1')) (a = '0' and b = '1')) THEN THEN yy <= '1'; <= '1'; ELSE ELSE yy <= <= 'X'; 'X'; --- could could also also be be ‘-’ ‘-’ END IF; END IF; END PROCESS END PROCESS comb; comb; END behavior; END behavior; 24/03/19 UAH-CPE528 50
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Slide #51.

After Clauses  Although not defined by the language, most simulator’s waveform windows do not show VHDL delta cycles adequately, if at all  Debugging large behavioral simulations before synthesis can be difficult if no delays are used - everything appears to happen simultaneously  List windows typically show delta cycles, but can be difficult to interpret  The solution is to put “dummy” delays in the behavioral descriptions using After clauses to “spread out” the events  After clauses are ignored for synhtesis CONSTANT CONSTANT delay delay :: TIME TIME := := 55 ns; ns; ... ... output output <= <= input input ++ 11 AFTER AFTER delay; delay; 24/03/19 UAH-CPE528 51
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Slide #52.

Inferring Latches  If signals or variables are not assigned values in some conditional expressions of IF or Case statements, level-sensitive sequential logic might result ARCHITECTURE ARCHITECTURE behavior behavior OF OF mux3_seq mux3_seq IS IS BEGIN BEGIN comb comb :: PROCESS(a,b,c,sel) PROCESS(a,b,c,sel) BEGIN BEGIN ENTITY mux3_seq is CASE ENTITY mux3_seq is CASE sel sel IS IS PORT(a : IN std_logic; WHEN "00" PORT(a : IN std_logic; WHEN "00" => => yy <= <= a; a; bb :: IN std_logic; WHEN "01" => y <= b; IN std_logic; WHEN "01" => y <= b; cc :: IN std_logic; WHEN IN std_logic; WHEN "10" "10" => => yy <= <= c; c; sel : IN std_logic_vector(1 DOWNTO 0); WHEN OTHERS => --empty sel : IN std_logic_vector(1 DOWNTO 0); WHEN OTHERS => --empty yy :: OUT std_logic); END OUT std_logic); END CASE; CASE; END mux3_seq; END PROCESS END mux3_seq; END PROCESS comb; comb; END behavior; END behavior; library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; 24/03/19 UAH-CPE528 52
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Slide #53.

Avioding Latches  library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; Assigning values of “don’t care” (‘X’ or ‘-’) in these cases can avoid this ENTITY ENTITY mux3 mux3 is is PORT(a : PORT(a : IN IN std_logic; std_logic; bb :: IN std_logic; IN std_logic; cc :: IN IN std_logic; std_logic; sel : IN std_logic_vector(1 sel : IN std_logic_vector(1 DOWNTO DOWNTO 0); 0); yy :: OUT std_logic); OUT std_logic); END mux3; END mux3; ARCHITECTURE ARCHITECTURE behavior behavior OF OF mux3 mux3 IS IS BEGIN BEGIN comb comb :: PROCESS(a,b,c,sel) PROCESS(a,b,c,sel) BEGIN BEGIN CASE CASE sel sel IS IS WHEN "00" WHEN "00" => => yy <= <= a; a; WHEN "01" => y <= b; WHEN "01" => y <= b; WHEN WHEN "10" "10" => => yy <= <= c; c; WHEN OTHERS => y <= WHEN OTHERS => y <= 'X'; 'X'; END CASE; END CASE; END PROCESS END PROCESS comb; comb; END behavior; END behavior; 24/03/19 UAH-CPE528 53
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Slide #54.

Problems to Avoid Inferring Latches in Complex Behaviors ARCHITECTURE ARCHITECTURE rtl rtl OF OF pc_comb pc_comb IS IS SIGNAL pc : unsigned(3 DOWNTO SIGNAL pc : unsigned(3 DOWNTO 0); 0); BEGIN BEGIN one one :: PROCESS(dat_in, PROCESS(dat_in, cntrl, cntrl, pc) pc) BEGIN ENTITY pc_comb IS BEGIN ENTITY pc_comb IS CASE PORT(data_in : IN unsigned(3 DOWNTO 0); CASE cntrl cntrl IS IS PORT(data_in : IN unsigned(3 DOWNTO 0); WHEN "01" cntrl : IN unsigned(1 DOWNTO 0); WHEN "01" => => pc pc <= <= (pc (pc ++ "0001") "0001" cntrl : IN unsigned(1 DOWNTO 0); WHEN "10" => pc <= pc; data_out : OUT unsigned(3 DOWNTO 0)); WHEN "10" => pc <= pc; data_out : OUT unsigned(3 DOWNTO 0)); WHEN END pc_comb; WHEN OTHERS OTHERS => => pc pc <= <= data_in; data_in; END pc_comb; END CASE; END CASE; END PROCESS END PROCESS one; one; DATA_OUT <= PC; DATA_OUT <= PC; END rtl; END rtl; library library IEEE; IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_1164.ALL; use use IEEE.numeric_std.ALL; IEEE.numeric_std.ALL; 24/03/19 UAH-CPE528 54
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Slide #55.

Problems to Avoid Synthesizing Asynchronous State Machines! library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; use use IEEE.numeric_std.all; IEEE.numeric_std.all; ARCHITECTURE ARCHITECTURE rtl rtl OF OF pc_comb2 pc_comb2 IS IS SIGNAL pc : unsigned(3 DOWNTO SIGNAL pc : unsigned(3 DOWNTO 0); 0); BEGIN BEGIN one one :: PROCESS(data_in, PROCESS(data_in, cntrl, cntrl, pc) pc) ENTITY pc_comb2 is BEGIN ENTITY pc_comb2 is BEGIN PORT(dat_in CASE PORT(dat_in :: IN IN unsigned(3 unsigned(3 DOWNTO DOWNTO 0); 0); CASE cntrl cntrl IS IS cntrl :: IN WHEN '1' => cntrl IN std_logic; std_logic; WHEN '1' => pc pc <= <= (pc (pc ++ "0001"); "0001"); data_out : OUT unsigned(3 DOWNTO 0)); WHEN '0' => pc <= data_in; data_out : OUT unsigned(3 DOWNTO 0)); WHEN '0' => pc <= data_in; END pc_comb2; WHEN END pc_comb2; WHEN OTHERS OTHERS => => pc pc <= <= "XXXX"; "XXXX"; END CASE; END CASE; END PROCESS END PROCESS one; one; dat_out <= pc; dat_out <= pc; END rtl; END rtl; 24/03/19 UAH-CPE528 55
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Slide #56.

Level Sensitive D Latch  Use IF statement without Else clause library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY d_latch d_latch is is PORT(d : IN PORT(d : IN std_logic; std_logic; clk : IN std_logic; clk : IN std_logic; qq :: INOUT INOUT std_logic; std_logic; qn : OUT std_logic); qn : OUT std_logic); END d_latch; END d_latch; ARCHITECTURE ARCHITECTURE behavior behavior OF OF d_latch d_latch IS IS BEGIN BEGIN seq seq :: PROCESS(d,clk) PROCESS(d,clk) BEGIN BEGIN IF(clk IF(clk == '1') '1') THEN THEN qq <= d; <= d; END IF; END IF; END PROCESS END PROCESS seq; seq; qn <= not q; qn <= not q; END behavior; END behavior; 24/03/19 UAH-CPE528 56
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Slide #57.

Master-Slave D Latch (D Flip-Flop) library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY ms_latch ms_latch is is PORT(d : IN PORT(d : IN std_logic; std_logic; clk : IN std_logic; clk : IN std_logic; qq :: INOUT INOUT std_logic; std_logic; qn : OUT std_logic); qn : OUT std_logic); END ms_latch; END ms_latch; ARCHITECTURE ARCHITECTURE behavior behavior OF OF ms_latch ms_latch IS IS SIGNAL q_int : std_logic; SIGNAL q_int : std_logic; BEGIN BEGIN seq1 seq1 :: PROCESS(d,clk) PROCESS(d,clk) BEGIN BEGIN IF(clk IF(clk == '1') '1') THEN THEN q_int <= d; q_int <= d; END END IF; IF; END PROCESS END PROCESS seq1; seq1; seq2 : PROCESS(q_int,clk) seq2 : PROCESS(q_int,clk) BEGIN BEGIN IF(clk IF(clk == '0') '0') THEN THEN qq <= q_int; <= q_int; END IF; END IF; END PROCESS END PROCESS seq2; seq2; qn <= not q; qn 24/03/19 <= not q; UAH-CPE528 END behavior; END behavior; Optimize 57
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Slide #58.

Edge Sensitive D Flip-Flop   Clocks must be of BIT or STD_LOGIC type - metalogic values not allowed Rising_edge() and Falling_edge() functions can be used to specify clock edge library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY d_ff d_ff is is PORT(d : PORT(d : IN IN std_logic; std_logic; clk : IN std_logic; clk : IN std_logic; qq :: INOUT INOUT std_logic; std_logic; qn : OUT std_logic); qn : OUT std_logic); END d_ff; END d_ff; ARCHITECTURE ARCHITECTURE behavior behavior OF OF d_ff d_ff IS IS BEGIN BEGIN seq seq :: PROCESS(clk) PROCESS(clk) BEGIN BEGIN IF(rising_edge(clk)) IF(rising_edge(clk)) THEN THEN qq <= d; <= d; END IF; END IF; END PROCESS END PROCESS seq; seq; qn <= not q; qn <= not q; END behavior; END 24/03/19 behavior; UAH-CPE528 58
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Slide #59.

Edge Sensitive D Flip-Flop (cont.)  Wait statement can be used library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ARCHITECTURE ARCHITECTURE behavior behavior OF OF d_ff_w d_ff_w IS IS BEGIN BEGIN seq seq :: PROCESS PROCESS BEGIN BEGIN WAIT WAIT UNTIL UNTIL clk clk == ‘1’; ‘1’; qq <= d; <= d; END PROCESS END PROCESS seq; seq; qn <= not q; qn <= not q; END behavior; END behavior; ENTITY ENTITY d_ff_w d_ff_w is is PORT(d : IN PORT(d : IN std_logic; std_logic; clk : IN std_logic; clk : IN std_logic; qq :: INOUT INOUT std_logic; std_logic; qn : OUT std_logic); qn : OUT std_logic); END d_ff_w; END d_ff_w; ARCHITECTURE ARCHITECTURE behavior behavior OF OF d_ff_w d_ff_w IS IS BEGIN BEGIN seq seq :: PROCESS PROCESS BEGIN BEGIN WAIT WAIT UNTIL UNTIL rising_edge(clk); rising_edge(clk); qq <= d; <= d; END PROCESS END PROCESS seq; seq; qn <= not q; qn <= not q; END behavior; END behavior; 24/03/19 UAH-CPE528 59
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Slide #60.

Edge Sensitive Flip-Flops library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY d_ff_pc d_ff_pc is is PORT(d : IN PORT(d : IN std_logic; std_logic; clk : IN std_logic; clk : IN std_logic; pre pre :: IN IN std_logic; std_logic; clr : IN std_logic; clr : IN std_logic; qq :: INOUT INOUT std_logic; std_logic; qn : OUT std_logic); qn : OUT std_logic); END d_ff_pc; END d_ff_pc;  Preset and clear functions can be added  Asynchronous with respect to the clock ARCHITECTURE ARCHITECTURE behavior behavior OF OF d_ff_pc d_ff_pc IS IS BEGIN BEGIN seq seq :: PROCESS(clk,pre,clr) PROCESS(clk,pre,clr) BEGIN BEGIN IF(pre IF(pre == '0') '0') THEN THEN qq <= '1'; <= '1'; ELSIF(clr ELSIF(clr == '0') '0') THEN THEN qq <= '0'; <= '0'; ELSIF(rising_edge(clk)) ELSIF(rising_edge(clk)) THEN THEN qq <= d; <= d; END IF; END IF; END PROCESS END PROCESS seq; seq; qn <= not q; qn <= not q; END behavior; END behavior; 24/03/19 UAH-CPE528 60
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Slide #61.

Edge Sensitive Flip-Flops library library IEEE; IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all; ENTITY ENTITY d_ff_spc d_ff_spc is is PORT(d : IN PORT(d : IN std_logic; std_logic; clk : IN std_logic; clk : IN std_logic; pre pre :: IN IN std_logic; std_logic; clr : IN std_logic; clr : IN std_logic; qq :: INOUT INOUT std_logic; std_logic; qn : OUT std_logic); qn : OUT std_logic); END d_ff_spc; END d_ff_spc;  Preset and clear functions can be added  Synchronous with respect to the clock ARCHITECTURE ARCHITECTURE behavior behavior OF OF d_ff_spc d_ff_spc IS IS BEGIN BEGIN seq seq :: PROCESS(clk) PROCESS(clk) BEGIN BEGIN IF(rising_edge(clk)) IF(rising_edge(clk)) THEN THEN IF(pre = '0') THEN IF(pre = '0') THEN qq <= <= '1'; '1'; ELSIF(clr ELSIF(clr == '0') '0') THEN THEN qq <= '0'; <= '0'; ELSE ELSE qq <= <= d; d; END IF; END IF; END END IF; IF; END PROCESS END PROCESS seq; seq; qn <= not q; qn 24/03/19 <= not q; UAH-CPE528 END behavior; END behavior; 61
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Slide #62.

Finite State Machine Synthesis  State machines can be modeled as a combinational portion and a sequential portion  Both Mealy and Moore type state machines can be described  Most synthesis tools employ special algorithms to minimize state machines - thus standard procedures must be used to enable the tool to recognize the state machine Huffman FSM Model Present State 24/03/19 Combinational Logic Memory Primary Inputs UAH-CPE528 Primary Outputs Next State 62
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Slide #63.

Mealy and Moore State Machine Models A state machine has three basic parts     Next State Logic Output Logic Memory The most straight-forward way to code a synthesizable state machine is to use one process per function Mealy Machine Model Primary Inputs Output Combinational Logic Moore Machine Model Primary Outputs Primary Inputs Next State Combinational Logic Memory Present State 24/03/19 Output Combinational Logic Primary Outputs Next State Combinational Logic Next State Present State UAH-CPE528 Memory  Next State 63
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