Sample Student Schedule Grade 9 English Social Studies Math Science Foreign Language Intro to Engineering Design Physical Education Grade 10 1 unit 1 unit 1 unit 1 unit 1 unit 1 unit .5 unit Grade 11 1 unit 1 unit 1 unit 1 unit 1 unit 1 unit .5 unit Grade 12 English Social Studies Math Science Digital Electronics 1 unit 1 unit 1 unit 1 unit *Computer Integrated Manufacturing 1 unit *Civil Engineer and Architecture *Biotechnical Engineering *Aerospace Engineering Physical Education English Social Studies Math Science Foreign Language Principles of Engineering Physical Education 1 unit .5 unit English Social Studies Math Science Engineering Design and Development Health Physical Education 1 unit 1 unit 1 unit 1 unit 1 unit .5 unit .5 unit
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CPE 631 AM MESI: CPU Requests CPU Read hit CPU Read BusRd / NoSh Invalid CPU Write /BusRdEx CPU Read miss BusRd / NoSh Exclusive CPU read miss BusWB, BusRd / NoSh CPU read miss BusWB, BusRd / NoSh CPU write hit /CPU read miss BusWB, BusRd / Sh CPU read hit CPU write hit Modified (read/write) 24/03/19 CPU read miss BusWB, BusRd / Sh CPU Write Miss BusRdEx CPU Write Hit BusInv UAH-CPE631 Shared CPU Read hit 4
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MESI: CPU Requests CPU Read hit CPU Read BusRd / NoSh Invalid CPU Write /BusRdEx CPU Read miss BusRd / NoSh Exclusive CPU read miss BusWB, BusRd / NoSh CPU read miss BusWB, BusRd / NoSh CPU write hit /- CPU read miss BusWB, BusRd / Sh CPU read hit CPU write hit Modified (read/write) 03/24/19 CPU read miss BusWB, BusRd / Sh CPU Write Miss BusRdEx CPU Write Hit BusInv UAH-CPE 631 Shared CPU Read hit 37
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Kiviat Graph for a Balanced System CPU CPU Only Busy Busy CPU/Channel Overlap CPU in Supervisor State CPU in Problem State CPU Channel only Busy Any Channel Wait Busy  Problem: Inter-related metrics     CPU busy = problem state + Supervisor state CPU wait = 100 – CPU busy Channel only – any channel –CPU/channel overlap CPU only = CPU busy – CPU/channel overlap 22
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Hardware Outline 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. Hardware Outline What is a Computer? Components of a Computer Categories of Computer Hardware Central Processing Unit (CPU) CPU Examples CPU Parts CPU: Control Unit CPU: Arithmetic/Logic Unit CPU: Registers How Registers Are Used Multicore Multicore History Storage Primary Storage Cache From Cache to the CPU Main Memory (RAM) Main Memory Layout RAM vs ROM Speed => Price => Size How Data Travel Between RAM and CPU Loading Data from RAM into the CPU 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. RAM is Slow Why Have Cache? Secondary Storage Media Types Speed, Price, Size CD-ROM & DVD-ROM CD-ROM & DVD-ROM: Disadvantage CD-ROM & DVD-ROM: Advantages Why Are Floppies So Expensive Per MB? I/O I/O: Input Devices I/O: Output Devices Bits Bytes Words Putting Bits Together Putting Bits Together (cont’d) Powers of 2 Powers of 2 vs Powers of 10 KB, MB, GB, TB, PB Kilo, Mega, Giga, Tera, Peta Moore’s Law Implication of Moore’s Law Double, double, … Hardware Lesson CS1313 Spring 2009 1
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15 Example Suppose we have two implementation of the same instruction set architecture. Machine “A” has a clock cycle time of 1 ns and a CPI of 2.0 for some program, and machine “B” has a clock cycle time of 2 ns and a CPI of 1.2 for the same program. Which machine is faster for this program and by how much? Both machines execute the same instructions for the program. Assume the number of instructions is “I”, CPU clock cycles (A) = I  2.0 CPU clock cycles (B) = I  1.2 The CPU time required for each machine is as follows: CPU time (A) = CPU clock cycles (A)  Clock cycle time (A) = I  2.0  1 ns = 2  I ns CPU time (B) = CPU clock cycles (B)  Clock cycle time (B) = I  1.2  2 ns = 2.4  I ns Therefore machine A will be faster by the following ratio: CPU Performanc e (A) CPU time (B) 2.4 ´I ns = = =1.2 CPU Performanc e (B) CPU time (A) 2 ´I ns
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CPU -Cache State Machine CPU Read hit • State machine for CPU requests for each memory block • Invalid state if in memory Invalidate Invalid CPU Write: Send Write Miss msg to h.d. Exclusive (read/writ) 03/24/19 CPU Read Send Read Miss message Fetch/Invalidate send Data Write Back message to home directory CPU read hit CPU write hit Shared (read/only) CPU read miss: Send Read Miss CPU Write:Send Write Miss message to home directory Fetch: send Data Write Back message to home directory CPU read miss: send Data Write Back message and read miss to home directory CPU write miss: send Data Write Back message and Write Miss to home UAH-CPE 631 directory 11
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CPE 631 AM CPU -Cache State Machine CPU Read hit   State machine for CPU requests Invalidate Shared for each Invalid (read/only) CPU Read memory block Send Read Miss Invalid state message CPU read miss: if in Send Read Miss CPU Write: memory Fetch/Invalidate send Data Write Back message to home directory Send Write Miss msg to h.d. Exclusive (read/writ) CPU read hit CPU write hit 24/03/19 CPU Write:Send Write Miss message to home directory Fetch: send Data Write Back message to home directory CPU read miss: send Data Write Back message and read miss to home directory CPU write miss: send Data Write Back message and Write Miss to home UAH-CPE631 directory 17
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CPU -Cache State Machine CPU Read hit • State machine for CPU requests for each memory block • Invalid state if in memory Invalidate Invalid Fetch/Invalidate send Data Write Back message to home directory CPU Read Send Read Miss message CPU read miss: Send Read Miss CPU Write: CPU Write:Send Send Write Miss Write Miss message msg to h.d. to home directory Exclusive (read/writ) CPU read hit CPU write hit 03/24/19 Shared (read/only) Fetch: send Data Write Back message to home directory CPU read miss: send Data Write Back message and read miss to home directory CPU write miss: send Data Write Back message and Write Miss to home UAH-CPE 631 directory 28
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CPE 631 AM CPU -Cache State Machine CPU Read hit   State machine for CPU requests Invalidate for each Invalid CPU Read memory block Send Read Miss Invalid state message if in CPU Write: memory Send Write Miss msg to h.d. Fetch/Invalidate send Data Write Back message to home directory Exclusive (read/writ) CPU read hit CPU write hit 24/03/19 Shared (read/only) CPU read miss: Send Read Miss CPU Write:Send Write Miss message to home directory Fetch: send Data Write Back message to home directory CPU read miss: send Data Write Back message and read miss to home directory CPU write miss: send Data Write Back message and Write Miss to home UAH-CPE631 directory 7
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CPU -Cache State Machine • State machine for CPU requests for each memory block • Invalid state if in memory Invalidate Invalid Fetch/Invalidate send Data Write Back message to home directory CPU read hit CPU write hit Shared (read/only) CPU Read Send Read Miss message CPU read miss: CPU Write: Send Read Miss Send Write Miss CPU Write: Send msg to h.d. Write Miss message to home directory Exclusive (read/write) 03/24/19 CPU Read hit Fetch: send Data Write Back message to home directory CPU read miss: send Data Write Back message and read miss to home directory CPU write miss: send Data Write Back message and Write Miss to home directory 60
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Case study Unit gene pools Unit 1: Unit 2: Unit 3: Unit 4: Unit 5: Unit 6: Unit 7: 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 Chromosome for the scheduling problem Unit 1 Unit 2 Unit 3 Unit 4 Unit 5 Unit 6 Unit 7 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 03/26/2019 Intelligent Systems and Soft Computing 41
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Issue Read command to I/O module Read status of I/O module Not ready CPU I/O Check status Issue Read command to I/O module I/O Read status of I/O module CPU I/O Check status Error condition Ready No CPU I/O Do something else Issue Read block command to I/O module Interrupt CPU Read status of DMA module Error condition I/O Write word into memory CPU CPU memory No Done? Yes Read word from I/O Module I/O Write word into memory CPU memory Done? Yes Next instruction (a) Programmed I/O Next instruction (b) Interrupt-driven I/O Figure7.4 ThreeTechniques for Input of a Block of Data © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. DMA (c) Direct memory access CPU DMA Do something else Interrupt Next instruction Ready Read word from I/O Module CPU CPU
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Snoopy-Cache State Machine • State machine for CPU requests for each cache block and for bus requests for each cache blockWrite miss Cache State 03/24/19 CPU Read hit Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus UAH-CPE 631 4
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CPE 631 AM Snoopy-Cache State Machine-III CPU Read hit State machine for CPU requests for each cache block and for bus requests for each cache block Cache State Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus 24/03/19 UAH-CPE631 3
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Snoopy-Cache State Machine-I • State machine for CPU requests for each cache block CPU Read hit Invalid CPU Read Place read miss on bus Shared (read/only) CPU Write Place Write Miss on bus CPU read miss CPU Read miss Write back block, Place read miss Place read miss on bus on bus CPU Write Place Write Miss on Bus Exclusive (read/write) CPU read hit CPU write hit 03/24/19 UAH-CPE 631 CPU Write Miss Write back cache block Place write miss on bus 8
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Snoopy-Cache State Machine-III • State machine for CPU requests for each cache block and for bus requests for each cache blockWrite miss Cache State 03/24/19 CPU Read hit Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus UAH-CPE 631 10
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Snoopy-Cache State Machine-I • State machine for CPU requests for each cache block CPU Read hit Invalid CPU Read Place read miss on bus Shared (read/only) CPU Write Place Write Miss on bus CPU read miss CPU Read miss Write back block, Place read miss Place read miss on bus on bus CPU Write Place Write Miss on Bus Exclusive (read/write) CPU read hit CPU write hit 03/24/19 UAH-CPE 631 CPU Write Miss Write back cache block Place write miss on bus 25
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Snoopy-Cache State Machine-III • State machine for CPU requests for each cache block and for bus requests for each cache blockWrite miss Cache State 03/24/19 CPU Read hit Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus UAH-CPE 631 27
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CPU -Cache State Machine CPU Read hit Invalidate Invalid Shared (read/only) CPU Read Send Read Miss message CPU Write: Send Write Miss msg to h.d. Fetch/Invalidate send Data Write Back message to home directory Exclusive (read/writ) CPU read hit CPU write hit CPU read miss: Send Read Miss CPU Write:Send Write Miss message to home directory Fetch: send Data Write Back message to home directory CPU read miss: send Data Write Back message and read miss to home directory CPU write miss: send Data Write Back message and Write Miss to home directory
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Block-replacement CPU Read hit • State machine for CPU requests for each cache block Invalid CPU Read Place read miss on bus Shared (read/only) CPU Write Place Write Miss on bus Cache Block State CPU read hit CPU write hit 03/24/19 CPU read miss CPU Read miss Write back block, Place read miss Place read miss on bus on bus CPU Write Place Write Miss on Bus Exclusive (read/write) CPU Write Miss Write back cache block Place write miss on bus 38
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Write-back State Machine-III CPU Read hit • State machine for CPU requests for each cache block and for bus requests for each cache block Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU read miss CPU Read miss for this block Write back block, Place read miss Write Back Place read miss on bus CPU Write Block; (abort on bus Place Write Miss on Bus memory access) Cache Block State CPU read hit CPU write hit 03/24/19 Exclusive (read/write) Read miss for this block Write Back Block; (abort memory access) CPU Write Miss Write back cache block Place write miss on bus 39
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Block-Replacement CPU Read hit • State machine for CPU requests Invalid for each cache block If must replace this block CPU Write Place Write Miss on bus Cache Block States CPU read hit CPU write hit 3/24+4/5-7/10 CPU Read Place read miss on bus Shared (read/only) CPU Read miss CPU read miss Place read miss Write back block, on bus Place read CPU Write miss on Place Write Miss on Bus bus Exclusive (read/write) CPU Write Miss Write back cache block Place write miss on bus CSE502-S10, Lec 16-18-SMP 37
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Write-back State Machine - All Requests CPU Read hit • State machine for CPU requests for each cache block and for bus requests for each cache block Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU Read miss CPU read miss for this block Place read miss Write Back Write back block, on bus Block; (abort Place read miss CPU Write memory on bus access) Place Write Miss on Bus Read miss Cache Block for this block Write Back States Exclusive Block; (abort (read/write) memory access) CPU read hit CPU Write Miss Write back cache block CPU write hit Place write miss on bus 38 3/24+4/5-7/10 CSE502-S10, Lec 16-18-SMP
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Experimental Results P.P.D. refers to peak power density Testcase Size 100 k 200 k 300 k 400 k 500 k P.P.D. CPU (s) P.P.D. CPU (s) P.P.D. CPU (s) P.P.D. CPU (s) P.P.D. CPU (s) Greedy 28.57 0.04 18.20 0.09 56.90 0.14 10.06 0.20 15.73 0.25 Our 2.20 1.09 2.83 2.38 3.41 3.90 4.94 5.23 5.36 6.59 Testcase Size 600 k 700 k 800 k 900 k 1000 k P.P.D. CPU (s) P.P.D. CPU (s) P.P.D. CPU (s) P.P.D. CPU (s) P.P.D. CPU (s) Greedy 99.08 0.31 39.76 0.38 72.13 0.47 72.99 0.49 38.08 0.62 Our 7.23 8.21 5.87 9.54 3.80 11.20 6.45 12.64 0.03 14.15 30
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