RAM vs. ROM   RAM - Random Access Memory (direct access) ROM - Read-Only Memory  The terms RAM and main memory are basically interchangeable  ROM could be a set of memory chips, or a separate device, such as a CD ROM  Both RAM and ROM are random (direct) access devices! RAM should probably be called Read-Write Memory  13
View full slide show




RAM vs. ROM • RAM - Random Access Memory (direct access) • ROM - Read-Only Memory • The terms RAM and main memory are basically interchangeable • ROM could be a set of memory chips, or a separate device, such as a CD ROM • Both RAM and ROM are random (direct) access devices! • RAM probably should be called Read-Write Memory © 2004 Pearson Addison-Wesley. All rights reserved 1-22
View full slide show




Producer Consumer Synchronized Circular Buffer Produced 1 into cell 0 write 1 read 0 buffer: Produced 2 into cell 1 write 2 read 0 buffer: Consumed 1 from cell 0 write 2 read 1 buffer: Produced 3 into cell 2 write 3 read 1 buffer: Produced 4 into cell 3 write 4 read 1 buffer: Produced 5 into cell 4 write 0 read 1 buffer: Produced 6 into cell 0 write 1 read 1 buffer: BUFFER FULL WAITING TO PRODUCE 7 Consumed 2 from cell 1 write 1 read 2 buffer: Produced 7 into cell 1 write 2 read 2 buffer: BUFFER FULL WAITING TO PRODUCE 8 Consumed 3 from cell 2 write 2 read 3 buffer: Produced 8 into cell 2 write 3 read 3 buffer: BUFFER FULL WAITING TO PRODUCE 9 Consumed 4 from cell 3 write 3 read 4 buffer: Produced 9 into cell 3 write 4 read 4 buffer: BUFFER FULL WAITING TO PRODUCE 10 Consumed 5 from cell 4 write 4 read 0 buffer: Produced 10 into cell 4 write 0 read 0 buffer: BUFFER FULL ProduceInteger finished producing values Terminating ProduceInteger 1 -1 -1 -1 -1 1 2 -1 -1 -1 1 2 -1 -1 -1 1 2 3 -1 -1 1 2 3 4 -1 1 2 3 4 5 6 2 3 4 5 Consumed 6 from cell 0 write 0 read 1 buffer: Consumed 7 from cell 1 write 0 read 2 buffer: Consumed 8 from cell 2 write 0 read 3 buffer: Consumed 9 from cell 3 write 0 read 4 buffer: Consumed 10 from cell 4 write 0 read 0 buffer: BUFFER EMPTY ConsumeInteger retrieved values totaling: 55 Terminating ConsumeInteger 6 6 6 6 6 6 2 3 4 5 6 7 3 4 5 6 7 3 4 5 6 7 8 4 5 6 7 8 4 5 6 7 8 9 5 6 7 8 9 5 6 7 8 9 10 7 7 7 7 7 8 8 8 8 8 9 9 9 9 9 10 10 10 10 10 Ref: http://userhome.brooklyn.cuny.edu/irudowdky/OperatingSystems.htm & Silberschatz, Gagne, & Galvin, Operating Systems Concepts, 7th ed, Wiley (ch 1-3)
View full slide show




set 51 35 14 00010 set 49 30 14 00010 set 47 32 13 00010 set 46 31 15 00010 set 50 36 14 00010 set 54 39 17 00100 set 46 34 14 00011 set 50 34 15 00010 set 44 29 14 00010 set 49 31 15 00001 set 54 37 15 00010 set 48 34 16 00010 set 48 30 14 00001 set 43 30 11 00001 set 58 40 12 00010 set 57 44 15 00100 set 54 39 13 00100 set 51 35 14 00011 set 57 38 17 00011 set 51 38 15 00011 set 54 34 17 00010 set 51 37 15 00100 set 46 36 10 00010 set 51 33 17 00101 set 48 34 19 00010 set 50 30 16 00010 set 50 34 16 00100 set 52 35 15 00010 set 52 34 14 00010 set 47 32 16 00010 set 48 31 16 00010 set 54 34 15 00100 set 52 41 15 00001 ver 56 42 30 14 45 set 55 001 011 01 ver 58 31 27 15 41 set 49 001 0010 ver 62 32 22 12 45 set 50 001 011 01 ver 56 35 25 13 39 set 55 001 00 11 01 ver 59 31 32 15 48 set 49 01 00010 ver 61 30 28 13 40 set 44 001 0101 ver 63 34 25 15 49 set 51 001 011 01 ver 61 35 28 13 47 set 50 001 010 10 ver 64 23 29 13 43 set 45 001 010 11 ver 66 32 30 13 44 set 44 001 011 00 ver 68 35 28 16 48 set 50 00111 00 ver 67 38 30 19 50 set 51 01 00 1001 ver 60 30 29 14 45 set 48 001 0111 57 38 35 ver 58 26 16 40 set 51 00001 010 111 0000 55 32 24 14 38 ver 50 23 33 set 46 00001 010 101 0110 55 37 24 15 37 ver 56 27 42 set 53 00001 010 111 0001 58 33 27 14 39 ver 57 30 42 set 50 ID PL PW SL DPP 2 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1s1 1 151 0 35 0 14 2 60 0 1 1 1 100 2 0 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 1s2 1 149 0 30 0 14 2 59 0 1 1 1 011 2 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1s3 1 047 1 32 0 13 2 60 0 1 1 1 100 2 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 1s4 1 146 1 31 0 15 2 58 0 1 1 1 010 2 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1s5 1 150 0 36 0 14 2 60 0 1 1 1 100 4 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0s6 0 054 1 39 0 17 4 58 0 1 1 1 010 3 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1s7 1 146 0 34 0 14 3 60 0 1 1 1 100 2 0 1 1 0 0 1 0 1 0 0 0 1 0 0 0 0 1s8 1 150 1 34 0 15 2 59 0 1 1 1 011 2 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1s9 1 144 0 29 0 14 2 59 0 1 1 1 011 1 0 1 1 0 0 0 1 0 1 1 1 1 1 0 0 0 1s10 1 149 1 31 0 15 1 58 0 1 1 1 010 2 0 1 1 0 1 1 0 1 0 0 1 0 1 0 0 0 1s11 1 154 1 37 0 15 2 60 0 1 1 1 100 2 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0s12 0 048 0 34 0 16 2 58 0 1 1 1 010 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1s13 1 148 0 30 0 14 1 59 0 1 1 1 011 1 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0 0 1s14 0 143 1 30 0 11 1 62 0 1 1 1 110 2 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1s15 1 058 0 40 0 12 2 63 0 1 1 1 111 4 0 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0 1s16 1 157 1 44 0 15 4 61 0 1 1 1 101 4 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 0 1s17 1 054 1 39 0 13 4 61 0 1 1 1 101 3 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1s18 1 151 0 35 0 14 3 60 0 1 1 1 100 3 0 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0s19 0 057 1 38 0 17 3 58 0 1 1 1 010 3 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1s20 1 151 1 38 0 15 3 60 0 1 1 1 100 2 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 1 0s21 0 054 1 34 0 17 2 57 0 1 1 1 001 4 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1s22 1 151 1 37 0 15 4 59 0 1 1 1 011 2 0 1 0 1 1 1 0 1 0 0 1 0 0 0 0 0 1s23 0 146 0 36 0 10 2 64 1 0 0 0 000 5 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 1 0s24 0 051 1 33 0 17 5 56 0 1 1 1 000 2 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0s25 0 148 1 34 0 19 2 56 0 1 1 1 000 2 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1 0s26 0 050 0 30 0 16 2 57 0 1 1 1 001 4 0 1 1 0 0 1 0 1 0 0 0 1 0 0 0 1 0s27 0 050 0 34 0 16 4 57 0 1 1 1 001 2 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 1s28 1 152 1 35 0 15 2 59 0 1 1 1 011 2 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1s29 1 152 0 34 0 14 2 60 0 1 1 1 100 2 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0s30 0 047 0 32 0 16 2 58 0 1 1 1 010 2 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0s31 0 048 0 31 0 16 2 57 0 1 1 1 001 4 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 0 1s32 1 154 1 34 0 15 4 58 0 1 1 1 010 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1s33 1 152 1 41 0 15 1 61 0 1 1 1 101 15 1111055 2 00111101101010 100111011100 0001001s34 01 42 0 14 2 62 0 1 1 1 110 10 1101049 1 00111101000110 001111101111 0001001s35 11 31 0 15 1 58 0 1 1 1 010 15 1110050 2 00111101011100 100100010100 0001001s36 01 32 0 12 2 61 0 1 1 1 101 11 0110155 2 00111101101010 100101001011 0001001s37 11 35 0 13 2 61 0 1 1 1 101 18 0101049 1 00111101000111 011010101010 0001011s38 10 31 0 15 1 58 0 1 1 1 e26 66 01 0 1 30 44 14 27 0 0 1 001 13 0 0 2 00110111110001 001111111000 00010011 s39 1 44 1 30 0 2 60 e27 28 13 48 14 230010111 11 01 068 1 34 15 0 0 2 00111101011111 100101001001 00010110 s40 1 1 51 1 0 15 2 59 e28 30 50 17 210010111 0 1 167 100 1 35 12 1 1 3 00111101011001 100101011010 00010010 s41 1 50 1 0 3 61 e29 29 13 45 15 260010111 1 0 160 13 1 23 3 01100010100010 001101111011 00010011 s42 100145 10 0 13 3 57 e30 57 26 35 10 360011101 00 10 100 14 1 2 01100010100100 100101010100 00010010 s43 1 44 1 32 0 13 2 60 e31 24 38 11 320011101 1 0 055 000 0 35 14 6 01101000011000 100101011010 00011100 s44 0 50 0 0 6 57 e32 24 16 37 10 330011101 0 0 155 17 151 0 38 4 01101000001111 100101111100 00011100 s45 0010 11 0 19 4 56 e33 58 27 39 12 320011101 00 00 0 0 15 1 1 1 3 00111101010000 001111111001 00010010 s46 1 1 48 0 30 0 14 3 58 e34 27 51 16 200010111 0 1 060 1 0 0 10 010 1 100101101100 00011000 1 1 12 1 0 2 001111010011 s47 0 0 51 0 38 0 2 59 e35 30 16 45 15 270010111 0 11 154 11 11100 1 100100 101 001 001 0 00010011 11046 0 32 10 010 2 0011011010 s48 01 0 14 2 59 e36 60 34 45 16 270010111 01 11 0 1 10 010 100 110 1 1001011001 011 0 00010011 0 1 0 13 0 2 00111101 s49 1 1 53 1 37 0 15 2 60 e37 31 47 15 240010111 1 00 067 101 0 10010101 00110 1 00010011 010 11150 1 33 12 2 001111010010 s50 00 0 14 2 60 0 1 1 1 IRIS(SL,SW,PL,PW)  DPPMinVec,MaxVEC vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 00 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 00 vir 00 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 01 vir 63 33 60 1001 58 27 51 0011 71 30 59 0101 63 29 56 0010 65 30 58 0110 76 30 66 0101 49 25 45 0001 73 29 63 0010 67 25 58 0010 72 36 61 1001 65 32 51 0100 64 27 53 0011 68 30 55 0101 57 25 50 0100 58 28 51 1000 64 32 53 0111 65 30 55 0010 77 38 67 0110 77 26 69 0111 60 22 50 1111 69 32 57 0111 56 28 49 0100 77 28 67 0100 63 27 49 0010 67 33 57 0101 72 32 60 0010 62 28 48 0010 61 30 49 0010 64 28 56 0101 72 30 58 0000 74 28 61 0011 79 38 64 0100 64 28 56 0110 63 28 51 1111 61 26 56 1110 77 30 61 0111 63 34 56 1000 64 31 55 0010 60 30 18 0010 69 31 54 0101 67 31 56 1000 69 31 51 0111 58 27 51 0011 68 32 59 25 19 21 18 22 21 17 18 18 25 20 19 21 20 24 23 18 22 23 15 23 20 20 18 21 18 18 18 21 16 19 20 22 15 14 23 24 18 18 21 24 23 19 23 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 i1 1 163 00 33 60 25 10 0 0 0 1010 1 i2 0 058 11 27 51 19 19 0 0 1 0011 1 i3 1 071 11 30 59 21 11 0 0 0 1011 1 i4 1 063 00 29 56 18 15 0 0 0 1111 1 i5 1 065 10 30 58 22 12 0 0 0 1100 0 i6 0 076 10 30 66 21 5 0 0 0 0101 0 i7 1 149 01 25 45 17 24 0 0 1 1000 1 i8 1 173 11 29 63 18 8 0 0 0 1000 1 i9 1 067 10 25 58 18 12 0 0 0 1100 1 i10 1 172 0 136 61 25 10 0 0 01010 1 i11 0 065 1 132 51 20 19 0 0 10011 1 i12 0 164 0 127 53 19 16 0 0 10000 1 i13 0 168 1 130 55 21 15 0 0 01111 1 i14 0 057 1 025 50 20 19 0 0 10011 1 i15 0 058 1 128 51 24 17 0 0 10001 1 i16 0 164 0 132 53 23 17 0 0 10001 1 i17 0 165 1 130 55 18 16 0 0 10000 0 i18 0 077 1 138 67 22 6 0 0 0 0110 0 i19 0 177 0 126 69 23 0 0 0 0 0000 1 e50 001 57028 41 13 30 0 0 11110 1 i1 1 063 01 33 60 25 10 0 0 0 1010 1 i2 0 058 01 27 51 19 19 0 0 1 0011 0 i3 0 071 11 30 59 21 11 0 0 0 1011 1 i4 0 063 01 29 56 18 15 0 0 0 1111 1 i5 1 065 01 30 58 22 12 0 0 0 1100 1 i6 1 176 00 30 66 21 5 0 0 0 0101 1 i7 0 049 00 25 45 17 24 0 0 1 1000 1 i8 0 073 01 29 63 18 8 0 0 0 1000 1 i9 1 067 00 25 58 18 12 0 0 0 1100 1 i10 1 072 1 036 61 25 10 0 0 01010 1 i11 1 165 0 132 51 20 19 0 0 10011 0 i12 0 064 0 027 53 19 16 0 0 10000 1 i13 1 068 0 030 55 21 15 0 0 01111 1 i14 0 057 1 125 50 20 19 0 0 10011 1 i15 1 058 0 028 51 24 17 0 0 10001 1 i16 1 164 0 132 53 23 17 0 0 10001 1 i17 1 065 0 030 55 18 16 0 0 10000 1 i18 0 177 1 138 67 22 6 0 0 0 0110 1 i19 0 077 1 026 69 23 0 0 0 0 0000 1 i40 0 169 1 031 54 21 16 0 0 10000 1 i41 1 067 0 031 56 24 13 0 0 01101 1 i42 0 069 1 131 51 23 18 0 0 10010 1 i43 0 058 1 127 51 19 19 0 0 10011 1 i44 1 068 1 132 59 23 11 0 0
View full slide show




set 0 set 0 set 0 set 0 set 0 set 0 set 1 set 0 set 0 set 1 set 0 set 0 set 1 set 1 set 0 set 0 set 0 set 1 set 1 set 1 set 0 set 0 set 0 set 1 set 0 set 0 set 0 set 0 set 0 set 0 set 0 set 0 set 1 set 0 set 1 set 0 set 0 set 1 set 0 set 0 set 1 set 1 set 0 set 0 set 0 set 1 SL 51 49 47 46 50 54 46 50 44 49 54 48 48 43 58 57 54 51 57 51 54 51 46 51 48 50 50 52 52 47 48 54 52 55 49 50 55 49 44 51 50 45 44 50 51 48 SW 35 30 32 31 36 39 34 34 29 31 37 34 30 30 40 44 39 35 38 38 34 37 36 33 34 30 34 35 34 32 31 34 41 42 31 32 35 31 30 34 35 23 32 35 38 30 PL PW 14 2 0 1 1 0 0 1 1 14 2 0 1 1 0 0 0 1 13 2 0 1 0 1 1 1 1 15 2 0 1 0 1 1 1 0 14 2 0 1 1 0 0 1 0 17 4 0 1 1 0 1 1 0 14 3 0 1 0 1 1 1 0 15 2 0 1 1 0 0 1 0 14 2 0 1 0 1 1 0 0 15 1 0 1 1 0 0 0 1 15 2 0 1 1 0 1 1 0 16 2 0 1 1 0 0 0 0 14 1 0 1 1 0 0 0 0 11 1 0 1 0 1 0 1 1 12 2 0 1 1 1 0 1 0 15 4 0 1 1 1 0 0 1 13 4 0 1 1 0 1 1 0 14 3 0 1 1 0 0 1 1 17 3 0 1 1 1 0 0 1 15 3 0 1 1 0 0 1 1 17 2 0 1 1 0 1 1 0 15 4 0 1 1 0 0 1 1 10 2 0 1 0 1 1 1 0 17 5 0 1 1 0 0 1 1 19 2 0 1 1 0 0 0 0 16 2 0 1 1 0 0 1 0 16 4 0 1 1 0 0 1 0 15 2 0 1 1 0 1 0 0 14 2 0 1 1 0 1 0 0 16 2 0 1 0 1 1 1 1 16 2 0 1 1 0 0 0 0 15 4 0 1 1 0 1 1 0 15 1 0 1 1 0 1 0 0 14 2 0 1 1 0 1 1 1 15 1 0 1 1 0 0 0 1 12 2 0 1 1 0 0 1 0 13 2 0 1 1 0 1 1 1 15 1 0 1 1 0 0 0 1 13 2 0 1 0 1 1 0 0 15 2 0 1 1 0 0 1 1 13 3 0 1 1 0 0 1 0 13 3 0 1 0 1 1 0 1 13 2 0 1 0 1 1 0 0 16 6 0 1 1 0 0 1 0 19 4 0 1 1 0 0 1 1 14 3 0 1 1 0 0 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 1 1 1 1 1 1 0 1 ver 0 ver 0 ver 0 ver 1 ver 0 ver 1 ver 1 ver 1 ver 1 vir 1 vir 1 vir 1 vir 0 vir 0 vir 1 vir 1 vir 0 vir 0 vir 1 vir 0 vir 1 vir 1 vir 0 vir 0 vir 1 vir 0 vir 0 vir 1 vir 1 vir 1 vir 0 vir 0 vir 0 vir 1 vir 0 vir 0 vir 0 vir 1 vir 0 vir 1 vir 0 vir 0 vir 1 vir 0 vir 1 vir 0 SL 61 58 50 56 57 57 62 51 57 63 58 71 63 65 76 49 73 67 72 65 64 68 57 58 64 65 77 77 60 69 56 77 63 67 72 62 61 64 72 74 79 64 63 61 77 63 SW 30 26 23 27 30 29 29 25 28 33 27 30 29 30 30 25 29 25 36 32 27 30 25 28 32 30 38 26 22 32 28 28 27 33 32 28 30 28 30 28 38 28 28 26 30 34 PL 46 40 33 42 42 42 43 30 41 60 51 59 56 58 66 45 63 58 61 51 53 55 50 51 53 55 67 69 50 57 49 67 49 57 60 48 49 56 58 61 64 56 51 56 61 56 PW 14 12 10 13 12 13 13 11 13 25 19 21 18 22 21 17 18 18 25 20 19 21 20 24 23 18 22 23 15 23 20 20 18 21 18 18 18 21 16 19 20 22 15 14 23 24 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 0 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 0 1 0 0 0 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 1 1 0
View full slide show




The 68HC11 Microcontroller Example 5.1 Using the following memory chips, how many SRAM chips will be needed to build a 512KB, 16-bit memory system for a 16-bit microprocessor? a. 256K × 1 SRAM b. 256K × 4 SRAM c. 256K × 8 SRAM d. 64K × 8 SRAM Solution: a. Sixteen SRAM chips with × 1 organization are needed to construct a 16-bit memory system. 16 256K × 1 chips are required to build a 512KB 16-bit memory system. b. Four SRAM chips with × 4 organization are needed to construct a 16-bit memory system. Four 256K × 4 SRAM chips are needed to construct a 512 KB 16-bit memory system. c. Two SRAM chips with × 8 organization are needed to construct a 16-bit memory system. Two 256K × 8 SRAM chips are needed to construct a 512 KB 16-bit memory system. d. Two SRAM chips with × 8 organization are needed to construct a 16-bit memory system. Eight 64K × 8 SRAM chips are needed to construct a 512 KB 16-bit memory system. H. Huang Transparency No.5-4
View full slide show




Not All 20 Point Fonts Are Equal 20  A - Can You Read B - Can You Read C - Can You Read D - Can You Read E - Can You Read F - Can You Read G - Can You Read H - Can You Read I - Can You Read 16  J - Can You Read K - Can You Read L - Can You Read M - Can You Read N - Can You Read O - Can You Read P - Can You Read Q - Can You Read R - Can You Read 14  J - Can You Read K - Can You Read L - Can You Read M - Can You Read O - Can You Read P - Can You Read Q - Can You Read R - Can You Read 12  J - Can You Read K - Can You Read L - Can You Read M - Can You Read N - Can You Read O - Can You Read P - Can You Read Q - Can You Read R - Can You Read My Students Tell Me That They Like The Readability Of Ariel Font I never use fonts smaller than 20 point for lecture.
View full slide show




Write-back State Machine-III CPU Read hit • State machine for CPU requests for each cache block and for bus requests for each cache block Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU read miss CPU Read miss for this block Write back block, Place read miss Write Back Place read miss on bus CPU Write Block; (abort on bus Place Write Miss on Bus memory access) Cache Block State CPU read hit CPU write hit 03/24/19 Exclusive (read/write) Read miss for this block Write Back Block; (abort memory access) CPU Write Miss Write back cache block Place write miss on bus 39
View full slide show




Write-back State Machine - All Requests CPU Read hit • State machine for CPU requests for each cache block and for bus requests for each cache block Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU Read miss CPU read miss for this block Place read miss Write Back Write back block, on bus Block; (abort Place read miss CPU Write memory on bus access) Place Write Miss on Bus Read miss Cache Block for this block Write Back States Exclusive Block; (abort (read/write) memory access) CPU read hit CPU Write Miss Write back cache block CPU write hit Place write miss on bus 38 3/24+4/5-7/10 CSE502-S10, Lec 16-18-SMP
View full slide show




CPE 631 AM Snoopy-Cache State Machine-III CPU Read hit State machine for CPU requests for each cache block and for bus requests for each cache block Cache State Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus 24/03/19 UAH-CPE631 3
View full slide show




Snoopy-Cache State Machine CPU Read hit Cache State Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus
View full slide show




Snoopy-Cache State Machine • State machine for CPU requests for each cache block and for bus requests for each cache blockWrite miss Cache State 03/24/19 CPU Read hit Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus UAH-CPE 631 4
View full slide show




Snoopy-Cache State Machine-III • State machine for CPU requests for each cache block and for bus requests for each cache blockWrite miss Cache State 03/24/19 CPU Read hit Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus UAH-CPE 631 10
View full slide show




Snoopy-Cache State Machine-III • State machine for CPU requests for each cache block and for bus requests for each cache blockWrite miss Cache State 03/24/19 CPU Read hit Write miss for this block Shared CPU Read Invalid (read/only) Place read miss on bus CPU Write Place Write Miss on bus CPU read miss CPU Read miss for this block Write back block, Place read miss Place read miss on bus Write Back CPU Write on bus Block; (abort Place Write Miss on Bus memory access) Block Read miss Write Back for this block Block; (abort Exclusive memory access) (read/write) CPU Write Miss CPU read hit Write back cache block CPU write hit Place write miss on bus UAH-CPE 631 27
View full slide show




Snoop Cache Extensions • Extensions: – Fourth State: Ownership Invalid Remote Write or Miss due to address conflict Write back block 03/24/19 Remote Write or Miss due to address conflict CPU Read Place read miss CPU Writeon bus Place Write Miss on bus Remote Read Write back CPU Write block Modified (read/write) CPU read hit CPU write hit CPU Read hit Shared (read/only) Remote – Clean exclusive state (no Read miss for private data on Place Data write) on Bus? Place Write Miss on Exclusive Bus (read/only) CPU Write Place Write Miss on Bus? – Shared-> Modified, need invalidate only (upgrade request), don’t read memory Berkeley Protocol MESI Protocol – Cache supplies data when shared state (no memory access) Illinois Protocol CPU Read hit UAH-CPE 631 18
View full slide show




III. RAM and ROM. Blocks of RAM (random access memory) or ROM (read-only memory) will sometimes be needed as part of our designs. A RAM or ROM memory cell will typically be implemented in simpler circuitry than a register cell. Memories will be addressed in fixed units (e.g., bytes or words), rather than one bit at a time. For both RAM and ROM if the memory contains N units, then log2N address lines will be needed. In addition, for RAM, a READ/WRITE line, to choose which is to be done, will be needed. M-bit input bus RAM or ROM Log2N-bit Address bus N locations; each location is M bits wide Read/Write (for RAM) M-bit output bus 33
View full slide show