04EI General Purpose Timer (GPT) Unit • • 27.9.2009 The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates three 16-bit timers. Each timer may operate independently in a number of different modes, or may be concatenated with another timer. • Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. • Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 0.4µs (at 20 MHZ). • The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. • Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/underflow. The state of this latch may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. • In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. D µ Embedded Systems Page 4
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Clocks and Timers  Provide current time, elapsed time, timer  Normal resolution about 1/60 second  Some systems provide higher-resolution timers  Programmable interval timer used for timings, periodic interrupts  ioctl() (on UNIX) covers odd aspects of I/O such as clocks and timers Operating System Concepts – 9th Edition 13.22 Silberschatz, Galvin and Gagne ©2013
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Clocks and Timers  Provide current time, elapsed time, timer  Programmable interval timer used for timings, periodic interrupts  ioctl() (on UNIX) covers odd aspects of I/O such as clocks and timers Operating System Concepts with Java – 8th Edition 12.39 Silberschatz, Galvin and Gagne ©2009
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Clocks and Timers  Provide current time, elapsed time, timer  Programmable interval timer used for timings, periodic interrupts  ioctl (on UNIX) covers odd aspects of I/O such as clocks and timers Operating System Concepts – 8th Edition 13.18 Silberschatz, Galvin and Gagne ©2009
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RELEASING CONNECTIONS The three-way handshake is also used to release an end-to-end connection, since it facilitates the detection of lost disconnect messages and/or ACKs. Disconnect Request (Start Sender Timer) Disconnect Request (Start Sender Timer) Disconnect Request (Start Receiver Timer) Disconnect Request (Start Receiver Timer) Disconnect ACK Disconnect ACK (Connection Released) Disconnect Request (Start Sender Timer) Disconnect Request (Start Receiver Timer) Disconnect Request (Start Sender Timer) Disconnect Request (Start Receiver Timer) Disconnect ACK (Connection Released) CS Disconnect Request (Start Sender Timer) Disconnect Request (Start Receiver Timer) Disconnect Request (Start Sender Timer) Disconnect Request (Start Sender Timer) Connection Disconnect Request Released (Start Sender Timer) When Timer Disconnect Request Expires N (Start Sender Timer) Times Chapter 3 Connection Released When Timer Expires Connection Released When Timer Expires Page 6
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Watchdog Timer-Interrupt Function The Watchdog Timer (WDT) uses two bits in the SFRs for interrupt control. The WDT interrupt flag (WDTIFG) (located in IFG1.0, initial state is reset) The WDT interrupt enable (WDTIE) (located in IE1.0, initial state is reset)  When using the watchdog mode, the WDTIFG flag is used by the reset interrupt service routine to determine if the watchdog caused the device to reset. If the flag is set, then the Watchdog Timer initiated the reset condition (either by timing out or by a security key violation). If the flag is cleared, then the PUC was caused by a different source. See chapter 3 for more details on the PUC and POR signals.  When using the Watchdog Timer in interval-timer mode, the WDTIFG flag is set after the selected time interval and a watchdog interval-timer interrupt is requested. The interrupt vector address in interval-timer mode is different from that in watchdog mode. In interval-timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced.  The WDTIE bit is used to enable or disable the interrupt from the Watchdog Timer when it is being used in interval-timer mode. Also, the GIE bit enables or disables the interrupt from the Watchdog Timer when it is being used in intervaltimer mode. CPE 323 8
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Watchdog Timer-Interrupt Function The Watchdog Timer (WDT) uses two bits in the SFRs for interrupt control. The WDT interrupt flag (WDTIFG) (located in IFG1.0, initial state is reset) The WDT interrupt enable (WDTIE) (located in IE1.0, initial state is reset)  When using the watchdog mode, the WDTIFG flag is used by the reset interrupt service routine to determine if the watchdog caused the device to reset. If the flag is set, then the Watchdog Timer initiated the reset condition (either by timing out or by a security key violation). If the flag is cleared, then the PUC was caused by a different source. See chapter 3 for more details on the PUC and POR signals.  When using the Watchdog Timer in interval-timer mode, the WDTIFG flag is set after the selected time interval and a watchdog interval-timer interrupt is requested. The interrupt vector address in interval-timer mode is different from that in watchdog mode. In interval-timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced.  The WDTIE bit is used to enable or disable the interrupt from the Watchdog Timer when it is being used in interval-timer mode. Also, the GIE bit enables or disables the interrupt from the Watchdog Timer when it is being used in intervaltimer mode. CPE 323 16
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GNU definition GNU = GNU not unix GNU = GNU not unix not unix GNU = GNU not unix not unix not unix GNU = GNU not unix not unix not unix not unix GNU = GNU not unix not unix not unix not unix not unix GNU = GNU (not unix) * (∞ + 1 ) Java Foundations, 3rd Edition, Lewis/DePasquale/Chase 5 - 10
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C:\UMBC\331\java> java.ext.dirs=C:\JDK1.2\JRE\lib\ext java.io.tmpdir=C:\WINDOWS\TEMP\ os.name=Windows 95 java.vendor=Sun Microsystems Inc. java.awt.printerjob=sun.awt.windows.WPrinterJob java.library.path=C:\JDK1.2\BIN;.;C:\WINDOWS\SYSTEM;C:\... java.vm.specification.vendor=Sun Microsystems Inc. sun.io.unicode.encoding=UnicodeLittle file.encoding=Cp1252 java.specification.vendor=Sun Microsystems Inc. user.language=en user.name=nicholas java.vendor.url.bug=http://java.sun.com/cgi-bin/bugreport... java.vm.name=Classic VM java.class.version=46.0 java.vm.specification.name=Java Virtual Machine Specification sun.boot.library.path=C:\JDK1.2\JRE\bin os.version=4.10 java.vm.version=1.2 java.vm.info=build JDK-1.2-V, native threads, symcjit java.compiler=symcjit path.separator=; file.separator=\ user.dir=C:\UMBC\331\java sun.boot.class.path=C:\JDK1.2\JRE\lib\rt.jar;C:\JDK1.2\JR... user.name=nicholas user.home=C:\WINDOWS C:\UMBC\331\java>java envSnoop -- listing properties -java.specification.name=Java Platform API Specification awt.toolkit=sun.awt.windows.WToolkit java.version=1.2 java.awt.graphicsenv=sun.awt.Win32GraphicsEnvironment user.timezone=America/New_York java.specification.version=1.2 java.vm.vendor=Sun Microsystems Inc. user.home=C:\WINDOWS java.vm.specification.version=1.0 os.arch=x86 java.awt.fonts= java.vendor.url=http://java.sun.com/ user.region=US file.encoding.pkg=sun.io java.home=C:\JDK1.2\JRE java.class.path=C:\Program Files\PhotoDeluxe 2.0\Adob... line.separator=
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Watchdog Timer General The primary function of the watchdog-timer module (WDT) is to perform a controlled-system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can work as an interval timer, to generate an interrupt after the selected time interval. Features of the Watchdog Timer include:  Eight software-selectable time intervals  Two operating modes: as watchdog or interval timer  Expiration of the time interval in watchdog mode, which generates a system reset; or in timer mode, which generates an interrupt request  Safeguards which ensure that writing to the WDT control register is only possible using a password  Support of ultralow-power using the hold mode Watchdog/Timer two functions:  SW Watchdog Mode  Interval Timer Mode CPE 323 3
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Watchdog Timer General The primary function of the watchdog-timer module (WDT) is to perform a controlled-system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can work as an interval timer, to generate an interrupt after the selected time interval. Features of the Watchdog Timer include:  Eight software-selectable time intervals  Two operating modes: as watchdog or interval timer  Expiration of the time interval in watchdog mode, which generates a system reset; or in timer mode, which generates an interrupt request  Safeguards which ensure that writing to the WDT control register is only possible using a password  Support of ultralow-power using the hold mode Watchdog/Timer two functions:  SW Watchdog Mode  Interval Timer Mode CPE 323 11
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Programmable Part Types Semiconductor manufacturers have developed several types of regular programmable logic elements. Three important ones are: 1. Read Only Memory (ROM) -- a fixed array of AND gates and a programmable array of OR gates. 2. Programmable Array Logic (PAL) -- a programmable array of AND gates feeding a fixed array of OR gates. 3. Programmable Logic Array (PLA) -- a programmable array of AND gates feeding a programmable array of OR gates. All of the above use regular structures of logic elements that can be thought of as a "memory array". There are also programmable devices that look more like programmable logic cells with programmable interconnect. SYEN 3330 Digital Systems Chapter 4-2 Page 4
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04EI General Purpose Timer 1 (GPT 1 - 20 MHz) • • • • • 27.9.2009 Drei 16-Bit Vor-/Rückwärts-Zähler: 1 Core Timer(T3) und 2 Auxiliary Timers (T2,T4) Takteingangssignale: – Timer Modus: Interner Takteingang mit Vorteiler bis zu 2.5 MHz / 400 ns; der Takt kann mit einem externen Signal verknüpft werden. – Counter Modus: Externer Takt bis zu 1.25 MHz. – Kaskadieren des Core-Timer mit jedem der Aux.-Timer (33-Bit timer). – Zählrichtung kann mittels Eingangssignal gewechselt werden. Ausgangssignale – Interrupt-Generierung und Signalwechsel durch den Core Timer T3. – Interrupt-Generierung durch die Auxiliary Timer T2 und T4. Reload: Der Core Timer kann mit dem Inhalt eines beliebigen Auxiliary Timer geladen werden. Capture: Der Inhalt des Core Timer kann in jeden der Auxiliary Timer übernommen werden. D µ Embedded Systems Seite 4
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Introduction to the new mainframe What is interrupt processing An interrupt is an event that alters the sequence in which the processor executes instructions. z/OS uses six types of interrupts, as follows: 1. Supervisor calls or SVC interrupts These occur when the program issues an SVC to request a particular system service. An SVC interrupts the program being executed and passes control to the supervisor so that it can perform the service. Programs request these services through macros, such as OPEN (open a file), GETMAIN (obtain storage), or WTO (write a message to the system operator). 2. I/O interrupts These occur when the channel subsystem signals a change of status, such as an I/O operation completing, an error occurring, or when an I/O device, such as a printer, has become ready for work. 3. External interrupts These can indicate any of several events, such as a time interval expiring, the operator pressing the interrupt key on the console, or the processor receiving a signal from another processor. 4. Restart interrupts These occur when the operator selects the restart function at the console or when a restart SIGP (signal processor) instruction is received from another processor. 5. Program interrupts These are caused by program errors (for example, the program attempts to perform an invalid operation), page faults (the program references a page that is not in central storage), or requests to monitor an event. 6. Machine check interrupts These are caused by machine malfunctions. © Copyright IBM Corp., 2010. All rights reserved. Page 70 of 85
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6.7.3 Searching and Replacing The following command sequence demonstrates the vi search and replacement capability: ❏ Type :/UNIX and press [Return] This searches forward to find the first occurrence of the word UNIX. ❏ Type cwunix and press [Return] This changes UNIX to unix. ❏ Type n This finds the next occurrence of the word UNIX. ❏ Press . (dot) This repeats the last change (UNIX to unix.) ❏ Type :?unix and press [Return] This searches backward from the current line to find the first occurrence of the word unix. ❏ Type dw This deletes the word unix. ❏ Type n This finds the next occurrence of the word unix. ❏ Press . (dot) This repeats the last command (dw) and delete the word unix. Amir Afzal UNIX Unbounded, 5th Edition Copyright ©2008 Chapter 6: The vi Editor – Last Look 53 of 55
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Keeping Track of the Working Set  Approximate with interval timer + a reference bit  Example:  = 10,000  Timer interrupts after every 5000 time units  Keep in memory 2 bits for each page  Whenever a timer interrupts copy and sets the values of all reference bits to 0  If one of the bits in memory = 1  page in working set  Why is this not completely accurate?  Improvement = 10 bits and interrupt every 1000 time units Operating System Concepts with Java – 8th Edition 9.49 Silberschatz, Galvin and Gagne ©2009
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04EI GPT 1 Summary (GPT 1 - 20 MHz) 12.08.2013 • Three 16-Bit up/down-counter: 1 Core Timer(T3) and 2 Auxiliary Timers (T2,T4) • Clock input signals: – Timer Modus: Internal clock input with prescaler up to 2.5 MHz / 400 ns; – Counter Modus: External clock up to 1.25 MHz. – Cascading of the Core-Timer with each of the Aux.-Timer (33-Bit timer). – Counting direction can be changed via input signal. • Output signals – Interrupt-generation and signal switching via Core Timer T3. – Interrupt-generation via Auxiliary Timer T2 and T4. • Reload: The Core Timer can be loaded with the content of any Auxiliary Timer. • Capture: The content of the Core Timer can be taken over to any Auxiliary Timer D µ Embedded Systems Page 5
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2009
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2009
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The ‘ioctl.c’ module • These techniques are demonstrated in this device-driver module’s ‘ioctl()’ function • Two IOCTL commands are implemented – #define CURSOR_HIDE – #define CURSOR_SHOW 0 1 • Applications can open the device-file, then use an ioctl-command; for example: int fd = open( “/dev/vram”, O_RDWR ); ioctl( fd, CURSOR_HIDE);
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Watchdog Timer-Timer Mode  Setting WDTCTL register bit TMSEL to 1 selects the timer mode. This mode provides periodic interrupts at the selected time interval. A time interval can also be initiated by writing a 1 to bit CNTCL in the WDTCTL register.  When the WDT is configured to operate in timer mode, the WDTIFG flag is set after the selected time interval, and it requests a standard interrupt service. The WDT interrupt flag is a single-source interrupt flag and is automatically reset when it is serviced. The enable bit remains unchanged. In interval-timer mode, the WDT interrupt-enable bit and the GIE bit must be set to allow the WDT to request an interrupt. The interrupt vector address in timer mode is different from that in watchdog mode. CPE 323 9
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Watchdog Timer-Timer Mode  Setting WDTCTL register bit TMSEL to 1 selects the timer mode. This mode provides periodic interrupts at the selected time interval. A time interval can also be initiated by writing a 1 to bit CNTCL in the WDTCTL register.  When the WDT is configured to operate in timer mode, the WDTIFG flag is set after the selected time interval, and it requests a standard interrupt service. The WDT interrupt flag is a single-source interrupt flag and is automatically reset when it is serviced. The enable bit remains unchanged. In interval-timer mode, the WDT interrupt-enable bit and the GIE bit must be set to allow the WDT to request an interrupt. The interrupt vector address in timer mode is different from that in watchdog mode. CPE 323 17
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