DMA Problems  With virtual memory systems: (pages would have physical and virtual addresses)  Physical pages re-mapping to different virtual pages during DMA operations  Multi-page DMA cannot assume consecutive addresses Solutions:  Allow virtual addressing based DMA  Add translation logic to DMA controller  OS allocated virtual pages to DMA prevent re-mapping until DMA completes  Partitioned DMA  Break DMA transfer into multi-DMA operations, each is single page  OS chains the pages for the requester  In cache-based systems: (there can be two copies of data items)  Processor might not know that the cache and memory pages are different  Write-back caches can overwrite I/O data or makes DMA to read wrong data Solutions:  Route I/O activities through the cache  Not efficient since I/O data usually is not demonstrating temporal locality  OS selectively invalidates cache blocks before I/O read or force write-back prior to I/O write  Usually called cache flushing and requires hardware support DMA DMA allows allows another another path path to to main main memory memory with with no no cache cache and and address address translation translation 10
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C:\UMBC\331\java> java.ext.dirs=C:\JDK1.2\JRE\lib\ext java.io.tmpdir=C:\WINDOWS\TEMP\ os.name=Windows 95 java.vendor=Sun Microsystems Inc. java.awt.printerjob=sun.awt.windows.WPrinterJob java.library.path=C:\JDK1.2\BIN;.;C:\WINDOWS\SYSTEM;C:\... java.vm.specification.vendor=Sun Microsystems Inc. sun.io.unicode.encoding=UnicodeLittle file.encoding=Cp1252 java.specification.vendor=Sun Microsystems Inc. user.language=en user.name=nicholas java.vendor.url.bug=http://java.sun.com/cgi-bin/bugreport... java.vm.name=Classic VM java.class.version=46.0 java.vm.specification.name=Java Virtual Machine Specification sun.boot.library.path=C:\JDK1.2\JRE\bin os.version=4.10 java.vm.version=1.2 java.vm.info=build JDK-1.2-V, native threads, symcjit java.compiler=symcjit path.separator=; file.separator=\ user.dir=C:\UMBC\331\java sun.boot.class.path=C:\JDK1.2\JRE\lib\rt.jar;C:\JDK1.2\JR... user.name=nicholas user.home=C:\WINDOWS C:\UMBC\331\java>java envSnoop -- listing properties -java.specification.name=Java Platform API Specification awt.toolkit=sun.awt.windows.WToolkit java.version=1.2 java.awt.graphicsenv=sun.awt.Win32GraphicsEnvironment user.timezone=America/New_York java.specification.version=1.2 java.vm.vendor=Sun Microsystems Inc. user.home=C:\WINDOWS java.vm.specification.version=1.0 os.arch=x86 java.awt.fonts= java.vendor.url=http://java.sun.com/ user.region=US file.encoding.pkg=sun.io java.home=C:\JDK1.2\JRE java.class.path=C:\Program Files\PhotoDeluxe 2.0\Adob... line.separator=
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Diploma Diploma VOCATIONAL/DIPLOMAPath VOCATIONAL/DIPLOMAPath DMA DMA 010-030 010-030 MAT MAT 110 110 Vocational Vocational AAS AAS Example Example Programs Programs -Construction Tech Construction Tech Computer Tech Computer Tech Electronics Electronics Tech Tech TECHPath TECHPath DMA DMA 010-050 010-050 (STEM) (STEM) MAT MAT 121 121 ** Example Example Programs Programs Engineering Engineering Tech Tech Architectural Architectural Tech Tech MAT MAT 122 122 MAT MAT 223 223 Advisement Advisement and and Assessment Assessment MAT MAT 172 172 ** CALCULUSPath CALCULUSPath DMA DMA 010-050 010-050 DMA 060-080 DMA 060-080 (STEM) (STEM) ** MAT MAT 171 171 AS AS Degree Degree (Some (Some requiring requiring higher higher math math courses) courses) Engineering, Engineering, Science, Science, Mathematics Mathematics MAT MAT 272, 272, 273, 273, 285 285 ** MAT MAT 263 263 OR OR Statistics Statistics (( MAT MAT 152) 152) Statistics Statistics (MAT (MAT 152) 152) QUANTPath QUANTPath DMA DMA 010-050 010-050 MAT MAT 271 271 AA-AS AA-AS Degrees Degrees Business Business Transfer Transfer AA AA Degree Degree Behavioral Behavioral & & Social Social Science Science Communication Communication AAS Example Programs AAS Example Programs Health Health Sciences? Sciences? Public Public Service? Service? QUANT QUANT Lit Lit ** (MAT (MAT 143) 143) AA AA Degree Degree AAS AAS Example Example Programs Programs Health Health Science Science Education Education Pubic Pubic Service Service
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DMA Transfer Cycle Times     DMA requires 1 or 2 MCLK cc to synchronize before each single transfer or complete block or burst-block transfer Each byte/word transfer requires 2 MCLK after synchronization, and one cycle of wait time after the transfer DMA cycle time is dependent on the MSP430 operating mode and clock system setup (use MCLK)   CPE 323 If the MCLK source is active, but the CPU is off, the DMA controller will use the MCLK source for each transfer, without re-enabling the CPU. If the MCLK source is off, the DMA controller will temporarily restart MCLK, sourced with DCOCLK, for the single transfer or complete block or burst-block transfer The CPU remains off, and after the transfer completes, MCLK is turned off. 11
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I/O Using DMA Memory Memory Memory-mapped I/O ROM Control Data transfer CPU CPU RAM I/O DMA     DMA DMA Controller Controller Interface Interface I/O I/O Peripheral Peripheral I/O I/O Peripheral Peripheral CPU sends device name, address, length and transfer direction to DMA controller (via memory-mapped I/O) CPU issues start command to DMA controller DMA controller provides handshake signals to I/O device & memory including addresses DMA controller interrupts processor when transfer is complete Spring 2016, arz CS555A – Real-Time Embedded Systems Stevens Institute of Technology 79
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I/O Using DMA Memory Memory Memory-mapped I/O ROM Control Data transfer CPU CPU RAM I/O DMA     DMA DMA Controller Controller Interface Interface I/O I/O Peripheral Peripheral I/O I/O Peripheral Peripheral CPU sends device name, address, length and transfer direction to DMA controller (via memory-mapped I/O) CPU issues start command to DMA controller DMA controller provides handshake signals to I/O device & memory including addresses DMA controller interrupts processor when transfer is complete Spring 2015, arz CS555A – Real-Time Embedded Systems Stevens Institute of Technology 15
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DMA Data – Fall 2013 Students Who Completed P R Course N % N % DMA-010 105 90.5 11 9.5 DMA-020 57 73.1 21 26.9 DMA-030 41 71.9 16 28.1 DMA-040 74 64.3 41 35.7 DMA-050 55 85.9 9 14.1 DMA-060 39 52.7 35 47.3 DMA-070 37 90.2 4 9.8 DMA-080 19 63.3 11 36.7 Total 427 74.3 148 25.7
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DMA Data – Spring 2014 Students Who Completed P R Course N % N % DMA-010 68 80 17 20 DMA-020 35 62.5 21 37.5 DMA-030 32 72.7 12 27.3 DMA-040 42 65.6 22 34.4 DMA-050 39 79.6 10 20.4 DMA-060 34 54.8 28 45.2 DMA-070 24 63.2 14 36.8 DMA-080 14 73.7 5 26.3 Total 288 69.1 129 30.9
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DMA overview (continued) • Engage the DMA engine for writing to memory by outputting 0x08 to the DMA Command Port • Clear the labeled bits in the DMA Status register • Place the command’s parameters into the appropriate IDE Command Block registers • Put command-code in IDE Command register • Activate the DMA data-transfer by outputting 0x09 to the DMA Command register • Then wait until the DMA Status register indicates that the DMA data-transfer has been completed
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2009
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2009
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts Essentials – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2011
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Contiguous Allocation (Cont)  Multiple-partition allocation  To allocate available memory to various processes waiting to be brought into memory  Hole – block of available memory; holes of various size are scattered throughout memory  When a process arrives, it is allocated memory from a hole large enough to accommodate it  Operating system maintains information in a table about: a) allocated partitions b) free partitions (hole) OS OS OS OS process 5 process 5 process 5 process 5 process 9 process 9 process 8 process 2 process 10 process 2 Operating System Concepts with Java – 8th Edition process 2 8.19 process 2 Silberschatz, Galvin and Gagne ©2009
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Principals of current accelerator-rich MPSoC 1. Input Done • ILP+HWACC 2.DMA Startcomposition – HW-ACC 3.DMA Done • Executes Compute-intense kernels/apps 4.DMA Start 5.DMA Done – ILP 6.ACC1 Start • Executes remaining 7.ACC1 Done applications • Orchestrates HWACCs / 8.DMA Start coordinate data movement 9.DMA Done 10.DMA Start memory – On-chip scratchpad (SPM) 11.DMA Done • Keeps data between ILP and 12.Output start ACCs on-chip – Avoid costly off-chip memory 13-Output accessDone 7
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