Common Functions of Interrupts  Interrupt transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines  Interrupt architecture must save the address of the interrupted instruction  Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt  A trap is a software-generated interrupt caused either by an error such as divide by 0 or a user request (system call).  An operating system is interrupt driven Operating System Concepts with Java – 8th Edition 1.11 Silberschatz, Galvin and Gagne ©2009
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Common Functions of Interrupts  Interrupt transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines  Interrupt architecture must save the address of the interrupted instruction  Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt  A trap is a software-generated interrupt caused either by an error or a user request  An operating system is interrupt driven Operating System Concepts – 8th Edition 1.12 Silberschatz, Galvin and Gagne ©2009
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C:\UMBC\331\java> java.ext.dirs=C:\JDK1.2\JRE\lib\ext java.io.tmpdir=C:\WINDOWS\TEMP\ os.name=Windows 95 java.vendor=Sun Microsystems Inc. java.awt.printerjob=sun.awt.windows.WPrinterJob java.library.path=C:\JDK1.2\BIN;.;C:\WINDOWS\SYSTEM;C:\... java.vm.specification.vendor=Sun Microsystems Inc. sun.io.unicode.encoding=UnicodeLittle file.encoding=Cp1252 java.specification.vendor=Sun Microsystems Inc. user.language=en user.name=nicholas java.vendor.url.bug=http://java.sun.com/cgi-bin/bugreport... java.vm.name=Classic VM java.class.version=46.0 java.vm.specification.name=Java Virtual Machine Specification sun.boot.library.path=C:\JDK1.2\JRE\bin os.version=4.10 java.vm.version=1.2 java.vm.info=build JDK-1.2-V, native threads, symcjit java.compiler=symcjit path.separator=; file.separator=\ user.dir=C:\UMBC\331\java sun.boot.class.path=C:\JDK1.2\JRE\lib\rt.jar;C:\JDK1.2\JR... user.name=nicholas user.home=C:\WINDOWS C:\UMBC\331\java>java envSnoop -- listing properties -java.specification.name=Java Platform API Specification awt.toolkit=sun.awt.windows.WToolkit java.version=1.2 java.awt.graphicsenv=sun.awt.Win32GraphicsEnvironment user.timezone=America/New_York java.specification.version=1.2 java.vm.vendor=Sun Microsystems Inc. user.home=C:\WINDOWS java.vm.specification.version=1.0 os.arch=x86 java.awt.fonts= java.vendor.url=http://java.sun.com/ user.region=US file.encoding.pkg=sun.io java.home=C:\JDK1.2\JRE java.class.path=C:\Program Files\PhotoDeluxe 2.0\Adob... line.separator=
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Introduction to Microprocessors and the Motorola 68HC11 Interrupts and Interrupt Routines • Interrupt Routines are a type of subroutine that gets executed when interrupts happen – 68HC11 stops, saves local state (content of all registers saved on the stack), processes the interrupt code, returns to main code exactly where it left off (no information is lost) – Interrupt servicing is automatic – Cannot interrupt an interrupt - interrupts are queued and processed sequentially • Interrupt Vector points to the starting address of the code associated with each interrupt – Upon an interrupt, 68HC11 finds its associated interrupt vector, then jumps to the address specified by the vector – Interrupt Vectors are mapped from $BFC0 through $BFFF on the Handy Board – 2 bytes needed for each vector ==> 32 total interrupt vectors – Location is predetermined • e.g., RESET vector is located at $BFFE and $BFFF (points to start of main code) Copyright Prentice Hall, 2001 13
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I/O Interrupt vs. Exception • An I/O interrupt is just like the exceptions except: – An I/O interrupt is asynchronous – Further information needs to be conveyed – Typically exceptions are more urgent than interrupts • An I/O interrupt is asynchronous with respect to instruction execution: – I/O interrupt is not associated with any instruction – I/O interrupt does not prevent any instruction from completion • You can pick your own convenient point to take an interrupt • I/O interrupt is more complicated than exception: – Needs to convey the identity of the device generating the interrupt – Interrupt requests can have different urgencies: • • • Interrupt request needs to be prioritized Priority indicates urgency of dealing with the interrupt high speed devices usually receive highest priority 8
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Interrupts  CPU Interrupt-request line (a wired in CPU hardware) triggered by I/O device  When the CPU detects that a controller has asserted a signal on the interrupt-request line, the CPU performs a state save and jump to the interrupt-handler routine at a fixed address in memory.  Maskable to ignore or delay some interrupts when CPU is executing something critical  Interrupt vector to dispatch interrupt to correct handler  Based on priority  Some nonmaskable  Interrupt mechanism also used for exceptions Operating System Concepts with Java – 8th Edition 12.29 Silberschatz, Galvin and Gagne ©2009
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Common Functions of Interrupts  Interrupt transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines  Interrupt architecture must save the address of the interrupted instruction  A trap or exception is a software-generated interrupt caused either by an error or a user request  An operating system is interrupt driven Operating System Concepts – 9th Edition 1.13 Silberschatz, Galvin and Gagne ©2013
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2009
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2009
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Interrupt Handling Upon detecting an interrupt signal, provided the particular interrupt or interrupt class is not masked, the CPU acknowledges the interrupt (so that the device can deassert its request signal) and begins executing an interrupt service routine. 1. Save the CPU state and call the interrupt service routine. 2. Disable all interrupts. 3. Save minimal information about the interrupt on the stack. 4. Enable interrupts (or at least higher priority ones). 5. Identify cause of interrupt and attend to the underlying request. 6. Restore CPU state to what existed before the last interrupt. 7. Return from interrupt service routine. The capability to handle nested interrupts is important in dealing with multiple high-speed I/O devices. Computer Architecture, Input/Output and Interfacing Slide 38
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Recall NIC’s interrupt registers enum { E1000_ICR E1000_ICS E1000_IMS E1000_IMC }; = 0x00C0, = 0x00C8, = 0x00D0, = 0x00D8, // Interrupt Cause Read // Interrupt Cause Set // Interrupt Mask Set // Interrupt Mask Clear Registers’ usage You use Interrupt Mask Set to selectively enable the NIC’s various interrupts; You use Interrupt Mask Clear to selectively disable any of the NIC’s interrupts; You use Interrupt Cause Read to find out which events have caused the NIC to generate an interrupt (and then you can ‘clear’ those bits by writing to ICR); You can write to the Interrupt Cause Set register to selectively trigger the NIC to generate any of its various interrupts -- provided they have been ‘enabled’ by bits being previously set in the NIC’s Interrupt Mask Register.
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I/O Interrupt ° An I/O interrupt is just like the exceptions except: • An I/O interrupt is asynchronous • Further information needs to be conveyed ° An I/O interrupt is asynchronous with respect to instruction execution: • I/O interrupt is not associated with any instruction • I/O interrupt does not prevent any instruction from completion - You can pick your own convenient point to take an interrupt ° I/O interrupt is more complicated than exception: • Needs to convey the identity of the device generating the interrupt • Interrupt requests can have different urgencies: - Interrupt request needs to be prioritized cs 152 buses.38 ©DAP & SIK 1995
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Interrupt Definitions • Interrupt – An event in hardware that triggers the processor to jump from its current program counter to a specific point in the code. • Interrupt Service Routine (ISR) – The function that is called or the particular assembly code that is executed when the interrupt happens is called the Interrupt Service Routine (ISR). • Interrupt flag (IFG) – this is the bit that is set that triggers the interrupt, leaving the interrupt resets this flag to the normal state. • Interrupt Enable – Control bit that tells the processor that a particular interrupt should or should not be ignored. • Interrupt Vector Table – A table in memory which maps ISRs to interrupts. SE-3910 - Dr. Josiah Yoder Slide style: Dr. Hornick Much Material: Dr. Schilling 3
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts Essentials – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2011
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Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Instr cache Reg file ALU Data cache Reg file Instr cache Reg file ALU Data cache Reg file Reg file ALU Data cache Instr 3 Instr 5 Instr 4 Instr cache Cycle 7 Cycle 8 Cycle 9 Cycle 2 Cycle 3 Writes into $8 Bubble Reg file Task dimension Cycle 4 ALU Bubble Instr cache Reg file Cycle 5 Cycle 6 Reg file Data cache Reg file ALU Data cache Reg file Cycle 8 Cycle 9 Cycle 7 Without data forwarding, three bubbles are needed to resolve a read-after-write data dependency Reads from $8 Time dimension Instr cache Instr 3 Instr 2 Instr 1 Bubble Instr cache Cycle 1 ALU Data cache Reg file Instr cache Reg file ALU Data cache Reg file ALU Data cache Reg file Reg file ALU Data cache Reg file Instr cache Reg file ALU Data cache Bubble Reg file Instr cache Task dimension Writes into $8 Reg file Instr cache Instr 4 Instr 5 Cycle 6 Time dimension Instr 2 Instr 1 Inserting Bubbles in a Pipeline Bubble Two bubbles, if we assume that a register can be updated and read from in one cycle Reads from $8 Reg file Computer Architecture, Data Path and Control Slide 48
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Operating-System Operations  Interrupt driven by hardware  Software error or request creates exception or trap  Division by zero, request for operating system service  Other process problems include infinite loop, processes modifying each other or the operating system  Dual-mode operation allows OS to protect itself and other system components  User mode and kernel mode  Mode bit provided by hardware  Provides ability to distinguish when system is running user code or kernel code  Some instructions designated as privileged, only executable in kernel mode  System call changes mode to kernel, return from call resets it to user Operating System Concepts with Java – 8th Edition 1.30 Silberschatz, Galvin and Gagne ©2009
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Operating Modes-General Another program flow may be selected by manipulating the data stored on the stack or the stack pointer. Being able to access the stack and stack pointer with the instruction set allows the program structures to be individually optimized, as illustrated in the following program flow: Enter interrupt routine The interrupt routine is entered and processed if an enabled interrupt awakens the MSP430:  The SR and PC are stored on the stack, with the content present at the interrupt event.  Subsequently, the operation mode control bits OscOff, SCG1, and CPUOff are cleared automatically in the status register. Return from interrupt Two different modes are available to return from the interrupt service routine and continue the flow of operation:  Return with low-power mode bits set. When returning from the interrupt, the program counter points to the next instruction. The instruction pointed to is not executed, since the restored low power mode stops CPU activity.  Return with low-power mode bits reset. When returning from the interrupt, the program continues at the address following the instruction that set the OscOff or CPUOff-bit in the status register. To use this mode, the interrupt service routine must reset the OscOff, CPUOff, SCGO, and SCG1 bits on the stack. Then, when the SR contents are popped from the stack upon RETI, the operating mode will be active mode (AM). CPE 323 17
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Interrupts  CPU Interrupt-request line triggered by I/O device  Interrupt handler receives interrupts  Maskable to ignore or delay some interrupts  Interrupt vector to dispatch interrupt to correct handler   Based on priority  Some nonmaskable Interrupt mechanism also used for exceptions Operating System Concepts – 8th Edition 13.8 Silberschatz, Galvin and Gagne ©2009
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Interrupt Handling  The operating system preserves the state of the CPU by storing registers and the program counter  Determines which type of interrupt has occurred:   polling  vectored interrupt system Separate segments of code determine what action should be taken for each type of interrupt Operating System Concepts – 8th Edition 1.13 Silberschatz, Galvin and Gagne ©2009
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