Interrupts  CPU Interrupt-request line (a wired in CPU hardware) triggered by I/O device  When the CPU detects that a controller has asserted a signal on the interrupt-request line, the CPU performs a state save and jump to the interrupt-handler routine at a fixed address in memory.  Maskable to ignore or delay some interrupts when CPU is executing something critical  Interrupt vector to dispatch interrupt to correct handler  Based on priority  Some nonmaskable  Interrupt mechanism also used for exceptions Operating System Concepts with Java – 8th Edition 12.29 Silberschatz, Galvin and Gagne ©2009
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Interrupts  CPU Interrupt-request line triggered by I/O device  Interrupt handler receives interrupts  Maskable to ignore or delay some interrupts  Interrupt vector to dispatch interrupt to correct handler   Based on priority  Some nonmaskable Interrupt mechanism also used for exceptions Operating System Concepts – 8th Edition 13.8 Silberschatz, Galvin and Gagne ©2009
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Interrupts   Polling can happen in 3 instruction cycles  Read status, logical-and to extract status bit, branch if not zero  How to be more efficient if non-zero infrequently? CPU Interrupt-request line triggered by I/O device   Interrupt handler receives interrupts   Checked by processor after each instruction Maskable to ignore or delay some interrupts Interrupt vector to dispatch interrupt to correct handler  Context switch at start and end  Based on priority  Some nonmaskable  Interrupt chaining if more than one device at same interrupt number Operating System Concepts – 9th Edition 13.10 Silberschatz, Galvin and Gagne ©2013
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Interrupt Handling Upon detecting an interrupt signal, provided the particular interrupt or interrupt class is not masked, the CPU acknowledges the interrupt (so that the device can deassert its request signal) and begins executing an interrupt service routine. 1. Save the CPU state and call the interrupt service routine. 2. Disable all interrupts. 3. Save minimal information about the interrupt on the stack. 4. Enable interrupts (or at least higher priority ones). 5. Identify cause of interrupt and attend to the underlying request. 6. Restore CPU state to what existed before the last interrupt. 7. Return from interrupt service routine. The capability to handle nested interrupts is important in dealing with multiple high-speed I/O devices. Computer Architecture, Input/Output and Interfacing Slide 38
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read write architecture behav_detailed of cpu-mem is Microprocessor-Memory Communication signal address: integer; signal data_in, data_out : word; (contd): A more detailed behavioral description signal data_read, data_write, mem_ready: std_logic := `0’; Shantanu Dutt, UIC CPU-Mem begin 6 6’ CMI: process is -- CPU-Memory Interface module data_read variable AR, PC : integer; variable data_reg, instr_reg: word; 3 3’ begin CPU-Mem data_write wait until read = ‘1’ or write = ‘1’; Interface 1 if read = ‘1’ then data_in dr 2 AR := PC; wait for 1 ns; -- 1 ns reg. acc. time 3 2 3’ 3 address <= AR after 2 ns; -- 2 ns prop. delay Memory PC address AR 3 data_read <= `1’ after 2 ns; -- 2ns prop. delay; note simult. w/ addr 4’ 4 4’ wait until mem_ready = ‘1’; 5 +2 data_out 5 instr_reg := data_out; wait for 1 ns; 6 IR <= instr_reg after 1 ns; ir 7’ 7 8 6 data_read <= `0’ after 2 ns; 4’ mem_ready 4 7’ wait until mem_ready = `0’; 8 PC := PC+2; wait for 1 ns; 6 1 DR ARin IR elsif write = ‘1’ then data_reg := DR; AR := ARin; Legend: dr: data_reg wait for 1 ns; -- 1 ns reg acc (both happening in parallel) ir: instr_reg address <= AR after 2 ns; data_in <= data_reg after 2 ns; The red arrows w/ #s show the seq. of operations (or of data_write <= ‘1’ after 2 ns; …………………… end if; corresp. signals). For a # j, j’ end process CMI; denotes the delayed version of CPU the corresp. signal Relate this Memory: process is seq. to the seq. of opers type data_type is array (0 to 63) of word; described in the VHDL code on variable store: data_type; variable temp_reg: word; the left. 2ns reg + 1ns reg (PC) variable addr: integer; RAM access 2ns prop. access delay begin 2ns prop. delay delay delay wait until data_read = `1’ or data_write = `1’; data_read 2ns prop. 3’ if data_read = ‘1’ then – next:1ns reg. & ram access delay for 2ns prop. addr :=address; temp_reg := store(addr/2); wait for 2 ns; read sig. delay mem_ready 4 data_out <= temp_reg after 2 ns; • Multi-process description describing fully responsive handshaking -- RAM r/w time is 1ns; prop. time = 2ns 4 mem_ready <= ‘1’ after 2 ns; between the CPU-Mem interface (CMI) and Memory modules • Most Data/address/control-signal propagation delays and storage 6’ wait until data_read = ‘0’; 7 mem_ready <= ‘0’ after 2 ns; access times are accounted for: delay parameters used: 1-way commun. elsif data_write = ‘1’ then addr := address; store(addr/2) := data_in; wait for 2 ns; ……………… end if; end process Memory; end architecture behav_detailed; time w/ memory = 2 ns, RAM/register r/w time = 1 ns. • Note: A safer form of wait until X = ‘1’ is if X /= ‘1’ then wait until X = ‘1’ when it is not known for sure that X will not be ‘1’ at the point we want to wait for X being ‘1’. Similarly for waiting for X to be ‘0’.
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The 8085 Interrupts • • • • When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine) The ‘EI’ instruction is a one byte instruction and is used to Enable the non-maskable interrupts. The ‘DI’ instruction is a one byte instruction and is used to Disable the non-maskable interrupts. The 8085 has a single Non-Maskable interrupt. – The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop. CSE 307 - Microprocessors Mohd. Moinul Hoque, Lecturer, CSE, AUST 5
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Interrupts • Interrupt is a process where an external device can get the attention of the microprocessor. – The process starts from the I/O device – The process is asynchronous. • Classification of Interrupts – Interrupts can be classified into two types: • Maskable Interrupts (Can be delayed or Rejected) • Non-Maskable Interrupts (Can not be delayed or Rejected) • Interrupts can also be classified into: • Vectored (the address of the service routine is hard-wired) • Non-vectored (the address of the service routine needs to be supplied externally by the device) CSE 307 - Microprocessors Mohd. Moinul Hoque, Lecturer, CSE, AUST 2
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Hardware interrupts • Maskable and non-maskable interrupts – Maskable: used for events that occur during regular operation conditions – Nonmaskable: reserved for extremely critical events – They are hardware mechanism for providing prompt services to external events. – Reduce real-time punctuality and make response times nondeterministic. • Processors provide two atomic instructions – EPI: enable priority interrupt (EPI) and – DPI: disable priority interrupt (DPI) 16
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Introduction to the new mainframe Storage areas in an address space z/OS V1R13 BAR Problem (user) programs Run here LINE CVT (offset 16 (hex10) within PSA) All storage above 2 GB This area is called high virtual storage and is addressable only by programs running in 64-bit mode. It is divided by the high virtual shared area, which is an area of installation-defined size that can be used to establish cross-address space viewable connections to obtained areas within this area. Extended areas above 16 MB This range of areas, which lies above the line (16 MB) but below the bar (2 GB), is a kind of “mirror image” of the common area below 16 MB. They have the same attributes as their equivalent areas below the line, but because of the additional storage above the line, their sizes are much larger. Nucleus This is a key 0, read-only area of common storage that contains operating system control programs. System queue area (SQA) (2048 MBs)This area contains system level (key 0) data accessed by multiple address spaces. The SQA area is not pageable (fixed), which means that it resides in central storage until it is freed by the requesting program. The size of the SQA area is predefined by the installation and cannot change while the operating system is active. Yet it has the unique ability to “overflow” into the CSA area as long as there is unused CSA storage that can be converted to SQA. Pageable link pack area (PLPA), fixed link pack area (FLPA), and modified link pack area (MLPA) This area contains the link pack areas (the pageable link pack area, fixed link pack area, and modified link pack area), which contain system level programs that are often run by multiple address spaces. For this reason, the link pack areas reside in the common area that is addressable by every address space, therefore eliminating the need for each address space to have its own copy of the program. This storage area is below the line and is therefore addressable by programs running in 24-bit mode. CSA This portion of common area storage (addressable by all address spaces) is available to all applications. The CSA is often used to contain data frequently accessed by multiple address spaces. The size of the CSA area is established at system initialization time (IPL) and cannot change while the operating system is active. LSQA/SWA/subpool 228/subpool 230 This assortment of subpools, each with specific attributes, is used primarily by system functions when the functions require address space level storage isolation. Being below the line, these areas are addressable by programs running in 24-bit mode. User Region This area is obtainable by any program running in the user’s address space, including user key programs. It resides below the line and is therefore addressable by programs running in 24-bit mode. System Region This small area (usually only four pages) is reserved for use by the region control task of each address space. Prefixed Save Area (PSA) This area is often referred to as “Low Core.” The PSA is a common area of virtual storage from address zero through 8191 in every address space. There is one unique PSA for every processor installed in a system. The PSA maps architecturally fixed hardware and software storage locations for the processor. Because there is a unique PSA for each processor, from the view of a program running on z/OS, the contents of the PSA can change any time the program is dispatched on a different processor. This feature is unique to the PSA area and is accomplished through a unique DAT manipulation technique called prefixing. © Copyright IBM Corp., 2010. All rights reserved. Page 42 of 85
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Common Functions of Interrupts  Interrupt transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines  Interrupt architecture must save the address of the interrupted instruction  Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt  A trap is a software-generated interrupt caused either by an error such as divide by 0 or a user request (system call).  An operating system is interrupt driven Operating System Concepts with Java – 8th Edition 1.11 Silberschatz, Galvin and Gagne ©2009
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