IEEE Reliability Test System 96-99 BUS 18 BUS 17 Total Load: 2,850 MW C BUS 21 BUS 23 A Plan Time Pe riod 0-72 h A Power G Energy Shed (MW) She d (MWh) 1,373 98,856 Total: 98,856 MWh 0-72 h 902 64,944 B 72-768 h 708 492,768 C 0-360 h BUS 16 230 kV A D B A A BUS 19 C B BUS 20 BUS 14 Synch. Cond. A BUS 13 BUS 15 E BUS 11 BUS 24 B Total: 557,712 MWh 756 BUS 22 272,160 BUS 12 B BUS 3 Total: 272,160 MW h C A BUS 9 BUS 10 BUS 6 cable BUS 4 F MW BUS 5 138 kV A B Attac +72h k C B +360h BUS 8 A cable BUS 7 +768h t BUS 1 BUS 2 Salmeron, Wood and Baldick (2004), IEEE 11 Transactions on Power Systems
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C:\UMBC\331\java> java.ext.dirs=C:\JDK1.2\JRE\lib\ext java.io.tmpdir=C:\WINDOWS\TEMP\ os.name=Windows 95 java.vendor=Sun Microsystems Inc. java.awt.printerjob=sun.awt.windows.WPrinterJob java.library.path=C:\JDK1.2\BIN;.;C:\WINDOWS\SYSTEM;C:\... java.vm.specification.vendor=Sun Microsystems Inc. sun.io.unicode.encoding=UnicodeLittle file.encoding=Cp1252 java.specification.vendor=Sun Microsystems Inc. user.language=en user.name=nicholas java.vendor.url.bug=http://java.sun.com/cgi-bin/bugreport... java.vm.name=Classic VM java.class.version=46.0 java.vm.specification.name=Java Virtual Machine Specification sun.boot.library.path=C:\JDK1.2\JRE\bin os.version=4.10 java.vm.version=1.2 java.vm.info=build JDK-1.2-V, native threads, symcjit java.compiler=symcjit path.separator=; file.separator=\ user.dir=C:\UMBC\331\java sun.boot.class.path=C:\JDK1.2\JRE\lib\rt.jar;C:\JDK1.2\JR... user.name=nicholas user.home=C:\WINDOWS C:\UMBC\331\java>java envSnoop -- listing properties -java.specification.name=Java Platform API Specification awt.toolkit=sun.awt.windows.WToolkit java.version=1.2 java.awt.graphicsenv=sun.awt.Win32GraphicsEnvironment user.timezone=America/New_York java.specification.version=1.2 java.vm.vendor=Sun Microsystems Inc. user.home=C:\WINDOWS java.vm.specification.version=1.0 os.arch=x86 java.awt.fonts= java.vendor.url=http://java.sun.com/ user.region=US file.encoding.pkg=sun.io java.home=C:\JDK1.2\JRE java.class.path=C:\Program Files\PhotoDeluxe 2.0\Adob... line.separator=
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46 Motor starting example • Below graph shows the bus voltages for starting the four motors three seconds apart 1.08 Bus 8 Bus 2 1.06 Bus 7 Bus 9 0.833 pu Bus 3 1.04 1.02 185 MW 0.909 pu 53 Mvar 1 0.98 0.882 pu Bus 5 39 MW 23 Mvar 37 MW 92 Mvar 0.888 pu 0 MW 0 MW 0 Mvar 0.901 pu 0.917 pu 0 Mvar Bus 6 0.912 pu 0.96 0.94 118 MW 42 Mvar 0.92 Bus 4 0.949 pu 86 MW 25 Mvar 0.9 0.88 Bus1 0.86 0.84 1.003 pu slack 0.82 0.8 0.78 0.76 0.74 0 2 4 g cb d fe g g 6 V pu_Bus Bus1 V pu_Bus Bus 4 V pu_Bus Bus 7 8 g g g 10 V pu_Bus Bus 2 V pu_Bus Bus 5 V pu_Bus Bus 8 12 g g g 14 16 V pu_Bus Bus 3 V pu_Bus Bus 6 V pu_Bus Bus 9 18 20 14 MW 94 Mvar 92 MW 27 Mvar
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Multiple Potential Bus Masters: the Need for Arbitration ° Bus arbitration scheme: • A bus master wanting to use the bus asserts the bus request • A bus master cannot use the bus until its request is granted • A bus master must signal to the arbiter after finish using the bus ° Bus arbitration schemes usually try to balance two factors: • Bus priority: the highest priority device should be serviced first • Fairness: Even the lowest priority device should never be completely locked out from the bus ° Bus arbitration schemes can be divided into four broad classes: • Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. • Distributed arbitration by collision detection: Ethernet uses this. • Daisy chain arbitration: see next slide. • Centralized, parallel arbitration: see next-next slide cs 152 buses.24 ©DAP & SIK 1995
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2009
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2009
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Virtual Machines  Operating System Debugging  Operating System Generation  System Boot Operating System Concepts Essentials – 8th Edition 2.2 Silberschatz, Galvin and Gagne ©2011
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The Course Mix • In 2013-14 MMCC ran 347 different course titles – 5 had more than 1,000 students enrolled – 301 had less than 100 students enrolled SPE.101 PSY.212 CIS.13 0 NUR.1 50 ECE.101 ART.1 15 MAT.2 17 PTA.1 05 ALH.212 PTA.1 26 ART.2 30 PSY.283 RAD.2 21 PSY.285 PED.103 BIS.12 6 HED.130 PSY.101 ECO.202 BIS.2 64 NUR.151 ART.135 BUS.231 WLD.130 PTA.106 ALH.213 PTA.130 CIS.1 32 SPE.105 RAD.226 AMS.126 PED.110 BIS.2 34 HED.134 MAT.104 PHL.201 HIS.102 GEL.101 MAT.126 MAT.102 BIS.138 PTA.110 PED.255 PTA.131 PSY.2 95 AMS.214 RAD.230 ACC.252 PHT.115 CIS.225 PED.119 CIS.10 0 PSY.205 BUS.162 NUR.1 21 WLD.125 ECE.112 BIS.25 0 PTA.111 AMS.125 PTA.140 SOC.250 AMS.223 HRA.1 98 CJS.223 ENG.225 ALH.125 PED.203 ENG.111 CHM.105 ACC.211 NUR.124 CIS.221 CIS.135 DRF.210 PTA.115 HRA.116 AMS.2 06 DRF.201 ART.240 HRA.220 BIO.11 0 SPE.205 NUR.133 PED.226 MAT.105 SPN.101 MAT.116 BUS.202 PSY.240 RAD.110 ART.2 15 PTA.1 16 ACC.251 AMS.22 2 HRA.102 CJS.222 ACC.205 BIO.201 DRF.2 50 HUM.251 ENG.202 ENG.222 HIS.21 1 ENG.112 HUM.102 BIS.142 IND.101 ECE.114 HUM.210 CHM.106 HRA.106 HRA.104 CJS.23 3 BUS.1 05 PHT.113 WLD.226 CIS.271 HIS.25 1 BIO.101 BIO.142 HIS.212 REL.111 PSY.281 IND.113 RAD.215 AMS.10 4 ALH.214 HRA.215 ART.245 PHY.212 CIS.2 90 PHT.114 ACC.280 ECE.150 MID.103 SOC.101 SSC.200 SOC.202 SOC.200 DRF.101 DRF.220 DRF.105 HRA.223 ALH.230 CJS.221 CIS.255 PHT.104 ECE.208 REL.2 91 ART.247 TAI.207 AMS.232 ENG.110 ENG.104 HUM.101 BIS.12 0 BIS.12 7 ALH.112 ART.2 35 WLD.126 RAD.1 15 EDU.290 CIS.26 0 PHT.1 05 PED.132 REL.292 BIS.23 8 TAI.20 8 AMS.232 ALH.10 0 POL.20 1 BIS.164 BIS.140 CJS.202 BIS.200 CJS.220 WLD.245 RAD.130 BIO.131 CJS.205 PHT.106 RAD.225 ART.206 CIS.295 MAT.230 WLD.227 MAT.21 2 MAT.12 4 NUR.22 1 NUR.12 5 SOC.289 CJS.204 PHY.103 BUS.225 AMS.124 BIO.245 HRA.10 5 RAD.20 0 PHL.210 BIS.230 SOC.291 HED.132 BUS.151 BIO.210 NUR.222 NUR.128 EDU.107 BIS.1 36 ART.137 CIS.1 75 HRA.108 MAT.060 HRA.204 RAD.201 SOC.222 ECE.207 TAI.2 77 NUR.132 ECO.20 1 HIS.223 NUR.223 NUR.152 PHY.101 BUS.25 0 ECE.1 13 ENG.205 HRA.205 ALH.22 0 HRA.285 HUM.183 SSC.1 11 JOR.120 MAT.226 PED.14 5 HUM.200 BUS.122 NUR.224 SPN.102 SPE.257 CJS.203 AMS.205 AMS.110 HRA.225 RAD.175 IND.116 BUS.241 AMS.116 MID.102 HED.136 WLD.246 PHL.220 ART.105 CHM.111 PSC.101 PTA.101 BIS.254 ART.211 ART.152 WLD.127 RAD.180 CIS.195 CJS.206 ART.236 PSY.103 ENG.206 ART.252 MAT.101 HED.1 15 DRF.120 NUR.228 NUR.127 SPN.201 BIS.240 ART.239 WLD.225 ENG.0 98 CJS.231 CJS.224 BIS.236 AMS.232 MID.1 01 BUS.289 HIS.10 1 MUS.275 NUR.227 ART.130 NUR.130 TAI.275 BIS.255 BUS.1 71 BIS.260 REL.290 CJS.23 2 ECE.201 BIO.135 ACC.2 61 PHL.250 CIS.280 SCI.20 0 SOC.220 NUR.2 25 CJS.200 NUR.1 34 PHY.211 BUS.255 FRN.101 CIS.27 0 DRF.280 ECE.20 2 GER.101 MAT.2 25 ART.254 HRA.2 15 CJS.203 BIO.141 BUS.153 NUR.226 BIO.100 MAT.170 IND.14 0 CJS.201 BIO.203 ALH.250 HRA.240 ECE.20 6 RAD.217 PHY.105 BUS.291 IND.10 2 FRN.102 ACC.201 ART.1 10 ECO.110 ANT.170 HUM.205 ART.2 05 CIS.19 0 CHM.112 PTA.1 25 ACC.231 ENG.213 RAD.2 20 POL.250 CIS.17 6 ART.2 41 PHY.1 06
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Chapter 2: Operating-System Structures  Operating System Services  User Operating System Interface  System Calls  Types of System Calls  System Programs  Operating System Design and Implementation  Operating System Structure  Operating System Debugging  System Boot Operating System Concepts – 9th Edition 2.2 Silberschatz, Galvin and Gagne
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A Two-Bus System Processor Memory Bus Processor Memory Bus Adaptor I/O Bus Bus Adaptor Bus Adaptor I/O Bus I/O Bus ° I/O buses tap into the processor-memory bus via bus adaptors: • Processor-memory bus: mainly for processor-memory traffic • I/O buses: provide expansion slots for I/O devices ° Apple Macintosh-II • NuBus: Processor, memory, and a few selected I/O devices • SCCI Bus: the rest of the I/O devices cs 152 buses.14 ©DAP & SIK 1995
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A Computer with two Bus System Processor Memory Bus Main memory Proces s or Bus Adaptor I/O Bus Bus Adaptor I/O Bus Bus Adaptor I/O Bus • I/O buses tap into the processor - memory bus via bus adaptors: – Processor - memory bus: mainly for processor - memory traffic – I/O buses: provide expansion slots for I/O devices • Example: Apple Macintosh II – NuBus: Processor, memory, and a few selected I/O devices – SCCI Bus: the rest of the I/O devices CSE 45432 SUNY New Paltz 15
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A Three-Bus System Processor Memory Bus Processor Memory Bus Adaptor Backplane Bus Bus Adaptor Bus Adaptor I/O Bus I/O Bus ° A small number of backplane buses tap into the processor-memory bus • Processor-memory bus is used for processor memory traffic • I/O buses are connected to the backplane bus ° Advantage: loading on the processor bus is greatly reduced cs 152 buses.15 ©DAP & SIK 1995
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4 Isochronous gen example • WSCC 9 bus from before, gen 3 dropping (85 MW) – Bus 2 No infinite bus, gen 1 is modeled with an isochronous generator (PW ISOGov1 model) Bus 7 Bus 8 Bus 9 Bus 3 60 163 MW 7 Mvar 1.016 pu 1.025 pu 1.026 pu 1.032 pu 1.025 pu 59.95 85 MW -11 Mvar 59.9 Bus 5 0.996 pu 100 MW Bus 6 59.85 1.013 pu 35 Mvar Bus 4 1.026 pu 90 MW 30 Mvar Bus1 1.040 pu slack 72 MW 27 Mvar Speed (Hz) 59.8 125 MW 50 Mvar 59.75 59.7 59.65 59.6 59.55 59.5 59.45 Gen 2 is modeled with a TGOV1 governor 59.4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Time (Seconds) b c d fe g Speed_Gen Bus 2 #1 g Case is wscc_9bus_ISOGOV Speed_Gen Bus 3 #1 g Speed_Gen Bus1 #1 19 20
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I/O Hardware   Incredible variety of I/O devices  Storage  Transmission  Human-interface Common concepts – signals from I/O devices interface with computer  Port – connection point for device  Bus - daisy chain or shared direct access   PCI bus common in PCs and servers, PCI Express (PCIe)  expansion bus connects relatively slow devices Controller (host adapter) – electronics that operate port, bus, device  Sometimes integrated  Sometimes separate circuit board (host adapter)  Contains processor, microcode, private memory, bus controller, etc – Some talk to per-device controller with bus controller, microcode, memory, etc Operating System Concepts – 9th Edition 13.5 Silberschatz, Galvin and Gagne ©2013
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Operating System Design and Implementation  Design and Implementation of OS not “solvable”, but some approaches have proven successful  Internal structure of different Operating Systems can vary widely  Start by defining goals and specifications  Affected by choice of hardware, type of system  User goals and System goals  User goals – operating system should be convenient to use, easy to learn, reliable, safe, and fast  System goals – operating system should be easy to design, implement, and maintain, as well as flexible, reliable, error-free, and efficient Operating System Concepts – 8th Edition 2.30 Silberschatz, Galvin and Gagne ©2009
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Operating System Design and Implementation  Design and Implementation of OS not “solvable”, but some approaches have proven successful  Internal structure of different Operating Systems can vary widely  Start by defining goals and specifications  Affected by choice of hardware, type of system  User goals and System goals  User goals – operating system should be convenient to use, easy to learn, reliable, safe, and fast  System goals – operating system should be easy to design, implement, and maintain, as well as flexible, reliable, error-free, and efficient Operating System Concepts – 8th Edition 2.27 Silberschatz, Galvin and Gagne ©2009
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A Computer with Three Bus System Processor Memory Bus Main memory Proces s or Backplane Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus • • • • A small number of backplane buses tap into the processor memory bus Advantage: Processor-memory bus can be made much faster than the backplane bus. I/O system can be expanded by plugging many I/O controllers and buses into the backplane without affecting the speed of processor-memory bus Example: IBM RS/6000 and Silicon Graphics Multiprocessors CSE 45432 SUNY New Paltz 16
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Chapter 1: Introduction  What Operating Systems Do  Computer-System Organization  Computer-System Architecture  Operating-System Structure  Operating-System Operations  Process Management  Memory Management  Storage Management  Protection and Security  Distributed Systems  Special-Purpose Systems  Computing Environments  Open-Source Operating Systems Operating System Concepts with Java – 8th Edition 1.2 Silberschatz, Galvin and Gagne ©2009
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